1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Xilinx ZynqMP DisplayPort DMA Controller Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyundescription: | 10*4882a593Smuzhiyun These bindings describe the DMA engine included in the Xilinx ZynqMP 11*4882a593Smuzhiyun DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3 12*4882a593Smuzhiyun channels for a video stream, 1 channel for a graphics stream, and 2 channels 13*4882a593Smuzhiyun for an audio stream). 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunmaintainers: 16*4882a593Smuzhiyun - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunallOf: 19*4882a593Smuzhiyun - $ref: "../dma-controller.yaml#" 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunproperties: 22*4882a593Smuzhiyun "#dma-cells": 23*4882a593Smuzhiyun const: 1 24*4882a593Smuzhiyun description: | 25*4882a593Smuzhiyun The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h 26*4882a593Smuzhiyun for a list of channel IDs). 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun compatible: 29*4882a593Smuzhiyun const: xlnx,zynqmp-dpdma 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun reg: 32*4882a593Smuzhiyun maxItems: 1 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun interrupts: 35*4882a593Smuzhiyun maxItems: 1 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun clocks: 38*4882a593Smuzhiyun description: The AXI clock 39*4882a593Smuzhiyun maxItems: 1 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun clock-names: 42*4882a593Smuzhiyun const: axi_clk 43*4882a593Smuzhiyun 44*4882a593Smuzhiyunrequired: 45*4882a593Smuzhiyun - "#dma-cells" 46*4882a593Smuzhiyun - compatible 47*4882a593Smuzhiyun - reg 48*4882a593Smuzhiyun - interrupts 49*4882a593Smuzhiyun - clocks 50*4882a593Smuzhiyun - clock-names 51*4882a593Smuzhiyun 52*4882a593SmuzhiyunadditionalProperties: false 53*4882a593Smuzhiyun 54*4882a593Smuzhiyunexamples: 55*4882a593Smuzhiyun - | 56*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun dma: dma-controller@fd4c0000 { 59*4882a593Smuzhiyun compatible = "xlnx,zynqmp-dpdma"; 60*4882a593Smuzhiyun reg = <0xfd4c0000 0x1000>; 61*4882a593Smuzhiyun interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 62*4882a593Smuzhiyun interrupt-parent = <&gic>; 63*4882a593Smuzhiyun clocks = <&dpdma_clk>; 64*4882a593Smuzhiyun clock-names = "axi_clk"; 65*4882a593Smuzhiyun #dma-cells = <1>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun... 69