1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/dma/st,stm32-dmamux.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: STMicroelectronics STM32 DMA MUX (DMA request router) bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Amelie Delaunay <amelie.delaunay@st.com> 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunallOf: 13*4882a593Smuzhiyun - $ref: "dma-router.yaml#" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun "#dma-cells": 17*4882a593Smuzhiyun const: 3 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun compatible: 20*4882a593Smuzhiyun const: st,stm32h7-dmamux 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun reg: 23*4882a593Smuzhiyun maxItems: 1 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun clocks: 26*4882a593Smuzhiyun maxItems: 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun resets: 29*4882a593Smuzhiyun maxItems: 1 30*4882a593Smuzhiyun 31*4882a593Smuzhiyunrequired: 32*4882a593Smuzhiyun - compatible 33*4882a593Smuzhiyun - reg 34*4882a593Smuzhiyun - dma-masters 35*4882a593Smuzhiyun 36*4882a593SmuzhiyununevaluatedProperties: false 37*4882a593Smuzhiyun 38*4882a593Smuzhiyunexamples: 39*4882a593Smuzhiyun - | 40*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 41*4882a593Smuzhiyun #include <dt-bindings/clock/stm32mp1-clks.h> 42*4882a593Smuzhiyun #include <dt-bindings/reset/stm32mp1-resets.h> 43*4882a593Smuzhiyun dma-router@40020800 { 44*4882a593Smuzhiyun compatible = "st,stm32h7-dmamux"; 45*4882a593Smuzhiyun reg = <0x40020800 0x3c>; 46*4882a593Smuzhiyun #dma-cells = <3>; 47*4882a593Smuzhiyun dma-requests = <128>; 48*4882a593Smuzhiyun dma-channels = <16>; 49*4882a593Smuzhiyun dma-masters = <&dma1 &dma2>; 50*4882a593Smuzhiyun clocks = <&timer_clk>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun... 54*4882a593Smuzhiyun 55