1*4882a593Smuzhiyun* Spreadtrum DMA controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding follows the generic DMA bindings defined in dma.txt. 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun- compatible: Should be "sprd,sc9860-dma". 7*4882a593Smuzhiyun- reg: Should contain DMA registers location and length. 8*4882a593Smuzhiyun- interrupts: Should contain one interrupt shared by all channel. 9*4882a593Smuzhiyun- #dma-cells: must be <1>. Used to represent the number of integer 10*4882a593Smuzhiyun cells in the dmas property of client device. 11*4882a593Smuzhiyun- #dma-channels : Number of DMA channels supported. Should be 32. 12*4882a593Smuzhiyun- clock-names: Should contain the clock of the DMA controller. 13*4882a593Smuzhiyun- clocks: Should contain a clock specifier for each entry in clock-names. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunExample: 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunController: 18*4882a593Smuzhiyunapdma: dma-controller@20100000 { 19*4882a593Smuzhiyun compatible = "sprd,sc9860-dma"; 20*4882a593Smuzhiyun reg = <0x20100000 0x4000>; 21*4882a593Smuzhiyun interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 22*4882a593Smuzhiyun #dma-cells = <1>; 23*4882a593Smuzhiyun #dma-channels = <32>; 24*4882a593Smuzhiyun clock-names = "enable"; 25*4882a593Smuzhiyun clocks = <&clk_ap_ahb_gates 5>; 26*4882a593Smuzhiyun}; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunClient: 30*4882a593SmuzhiyunDMA clients connected to the Spreadtrum DMA controller must use the format 31*4882a593Smuzhiyundescribed in the dma.txt file, using a two-cell specifier for each channel. 32*4882a593SmuzhiyunThe two cells in order are: 33*4882a593Smuzhiyun1. A phandle pointing to the DMA controller. 34*4882a593Smuzhiyun2. The slave id. 35*4882a593Smuzhiyun 36*4882a593Smuzhiyunspi0: spi@70a00000{ 37*4882a593Smuzhiyun ... 38*4882a593Smuzhiyun dma-names = "rx_chn", "tx_chn"; 39*4882a593Smuzhiyun dmas = <&apdma 11>, <&apdma 12>; 40*4882a593Smuzhiyun ... 41*4882a593Smuzhiyun}; 42