1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/dma/socionext,uniphier-mio-dmac.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: UniPhier Media IO DMA controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyundescription: | 10*4882a593Smuzhiyun This works as an external DMA engine for SD/eMMC controllers etc. 11*4882a593Smuzhiyun found in UniPhier LD4, Pro4, sLD8 SoCs. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunmaintainers: 14*4882a593Smuzhiyun - Masahiro Yamada <yamada.masahiro@socionext.com> 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunallOf: 17*4882a593Smuzhiyun - $ref: "dma-controller.yaml#" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunproperties: 20*4882a593Smuzhiyun compatible: 21*4882a593Smuzhiyun const: socionext,uniphier-mio-dmac 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun reg: 24*4882a593Smuzhiyun maxItems: 1 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun interrupts: 27*4882a593Smuzhiyun description: | 28*4882a593Smuzhiyun A list of interrupt specifiers associated with the DMA channels. 29*4882a593Smuzhiyun The number of interrupt lines is SoC-dependent. 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun clocks: 32*4882a593Smuzhiyun maxItems: 1 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun resets: 35*4882a593Smuzhiyun maxItems: 1 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun '#dma-cells': 38*4882a593Smuzhiyun description: The single cell represents the channel index. 39*4882a593Smuzhiyun const: 1 40*4882a593Smuzhiyun 41*4882a593Smuzhiyunrequired: 42*4882a593Smuzhiyun - compatible 43*4882a593Smuzhiyun - reg 44*4882a593Smuzhiyun - interrupts 45*4882a593Smuzhiyun - clocks 46*4882a593Smuzhiyun - '#dma-cells' 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunadditionalProperties: false 49*4882a593Smuzhiyun 50*4882a593Smuzhiyunexamples: 51*4882a593Smuzhiyun - | 52*4882a593Smuzhiyun // In the example below, "interrupts = <0 68 4>, <0 68 4>, ..." is not a 53*4882a593Smuzhiyun // typo. The first two channels share a single interrupt line. 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun dmac: dma-controller@5a000000 { 56*4882a593Smuzhiyun compatible = "socionext,uniphier-mio-dmac"; 57*4882a593Smuzhiyun reg = <0x5a000000 0x1000>; 58*4882a593Smuzhiyun interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, 59*4882a593Smuzhiyun <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>; 60*4882a593Smuzhiyun clocks = <&mio_clk 7>; 61*4882a593Smuzhiyun resets = <&mio_rst 7>; 62*4882a593Smuzhiyun #dma-cells = <1>; 63*4882a593Smuzhiyun }; 64