1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: SiFive Unleashed Rev C000 Platform DMA 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Green Wan <green.wan@sifive.com> 11*4882a593Smuzhiyun - Palmer Debbelt <palmer@sifive.com> 12*4882a593Smuzhiyun - Paul Walmsley <paul.walmsley@sifive.com> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyundescription: | 15*4882a593Smuzhiyun Platform DMA is a DMA engine of SiFive Unleashed. It supports 4 16*4882a593Smuzhiyun channels. Each channel has 2 interrupts. One is for DMA done and 17*4882a593Smuzhiyun the other is for DME error. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun In different SoC, DMA could be attached to different IRQ line. 20*4882a593Smuzhiyun DT file need to be changed to meet the difference. For technical 21*4882a593Smuzhiyun doc, 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun https://static.dev.sifive.com/FU540-C000-v1.0.pdf 24*4882a593Smuzhiyun 25*4882a593Smuzhiyunproperties: 26*4882a593Smuzhiyun compatible: 27*4882a593Smuzhiyun items: 28*4882a593Smuzhiyun - const: sifive,fu540-c000-pdma 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun reg: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun interrupts: 34*4882a593Smuzhiyun minItems: 1 35*4882a593Smuzhiyun maxItems: 8 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun '#dma-cells': 38*4882a593Smuzhiyun const: 1 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunrequired: 41*4882a593Smuzhiyun - compatible 42*4882a593Smuzhiyun - reg 43*4882a593Smuzhiyun - interrupts 44*4882a593Smuzhiyun - '#dma-cells' 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunadditionalProperties: false 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunexamples: 49*4882a593Smuzhiyun - | 50*4882a593Smuzhiyun dma@3000000 { 51*4882a593Smuzhiyun compatible = "sifive,fu540-c000-pdma"; 52*4882a593Smuzhiyun reg = <0x3000000 0x8000>; 53*4882a593Smuzhiyun interrupts = <23 24 25 26 27 28 29 30>; 54*4882a593Smuzhiyun #dma-cells = <1>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun... 58