1*4882a593SmuzhiyunQCOM BAM DMA controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: must be one of the following: 5*4882a593Smuzhiyun * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084 6*4882a593Smuzhiyun * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960 7*4882a593Smuzhiyun * "qcom,bam-v1.7.0" for MSM8916 8*4882a593Smuzhiyun- reg: Address range for DMA registers 9*4882a593Smuzhiyun- interrupts: Should contain the one interrupt shared by all channels 10*4882a593Smuzhiyun- #dma-cells: must be <1>, the cell in the dmas property of the client device 11*4882a593Smuzhiyun represents the channel number 12*4882a593Smuzhiyun- clocks: required clock 13*4882a593Smuzhiyun- clock-names: must contain "bam_clk" entry 14*4882a593Smuzhiyun- qcom,ee : indicates the active Execution Environment identifier (0-7) used in 15*4882a593Smuzhiyun the secure world. 16*4882a593Smuzhiyun- qcom,controlled-remotely : optional, indicates that the bam is controlled by 17*4882a593Smuzhiyun remote proccessor i.e. execution environment. 18*4882a593Smuzhiyun- num-channels : optional, indicates supported number of DMA channels in a 19*4882a593Smuzhiyun remotely controlled bam. 20*4882a593Smuzhiyun- qcom,num-ees : optional, indicates supported number of Execution Environments 21*4882a593Smuzhiyun in a remotely controlled bam. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun uart-bam: dma@f9984000 = { 26*4882a593Smuzhiyun compatible = "qcom,bam-v1.4.0"; 27*4882a593Smuzhiyun reg = <0xf9984000 0x15000>; 28*4882a593Smuzhiyun interrupts = <0 94 0>; 29*4882a593Smuzhiyun clocks = <&gcc GCC_BAM_DMA_AHB_CLK>; 30*4882a593Smuzhiyun clock-names = "bam_clk"; 31*4882a593Smuzhiyun #dma-cells = <1>; 32*4882a593Smuzhiyun qcom,ee = <0>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunDMA clients must use the format described in the dma.txt file, using a two cell 36*4882a593Smuzhiyunspecifier for each channel. 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunExample: 39*4882a593Smuzhiyun serial@f991e000 { 40*4882a593Smuzhiyun compatible = "qcom,msm-uart"; 41*4882a593Smuzhiyun reg = <0xf991e000 0x1000> 42*4882a593Smuzhiyun <0xf9944000 0x19000>; 43*4882a593Smuzhiyun interrupts = <0 108 0>; 44*4882a593Smuzhiyun clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 45*4882a593Smuzhiyun <&gcc GCC_BLSP1_AHB_CLK>; 46*4882a593Smuzhiyun clock-names = "core", "iface"; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun dmas = <&uart-bam 0>, <&uart-bam 1>; 49*4882a593Smuzhiyun dma-names = "rx", "tx"; 50*4882a593Smuzhiyun }; 51