1*4882a593Smuzhiyun* NVIDIA Tegra Audio DMA (ADMA) controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Tegra Audio DMA controller that is used for transferring data 4*4882a593Smuzhiyunbetween system memory and the Audio Processing Engine (APE). 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: Should contain one of the following: 8*4882a593Smuzhiyun - "nvidia,tegra210-adma": for Tegra210 9*4882a593Smuzhiyun - "nvidia,tegra186-adma": for Tegra186 and Tegra194 10*4882a593Smuzhiyun- reg: Should contain DMA registers location and length. This should be 11*4882a593Smuzhiyun a single entry that includes all of the per-channel registers in one 12*4882a593Smuzhiyun contiguous bank. 13*4882a593Smuzhiyun- interrupts: Should contain all of the per-channel DMA interrupts in 14*4882a593Smuzhiyun ascending order with respect to the DMA channel index. 15*4882a593Smuzhiyun- clocks: Must contain one entry for the ADMA module clock 16*4882a593Smuzhiyun (TEGRA210_CLK_D_AUDIO). 17*4882a593Smuzhiyun- clock-names: Must contain the name "d_audio" for the corresponding 18*4882a593Smuzhiyun 'clocks' entry. 19*4882a593Smuzhiyun- #dma-cells : Must be 1. The first cell denotes the receive/transmit 20*4882a593Smuzhiyun request number and should be between 1 and the maximum number of 21*4882a593Smuzhiyun requests supported. This value corresponds to the RX/TX_REQUEST_SELECT 22*4882a593Smuzhiyun fields in the ADMA_CHn_CTRL register. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyunadma: dma@702e2000 { 28*4882a593Smuzhiyun compatible = "nvidia,tegra210-adma"; 29*4882a593Smuzhiyun reg = <0x0 0x702e2000 0x0 0x2000>; 30*4882a593Smuzhiyun interrupt-parent = <&tegra_agic>; 31*4882a593Smuzhiyun interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 32*4882a593Smuzhiyun <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 33*4882a593Smuzhiyun <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 34*4882a593Smuzhiyun <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 35*4882a593Smuzhiyun <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 36*4882a593Smuzhiyun <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 37*4882a593Smuzhiyun <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 38*4882a593Smuzhiyun <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 39*4882a593Smuzhiyun <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 40*4882a593Smuzhiyun <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 41*4882a593Smuzhiyun <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 42*4882a593Smuzhiyun <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 43*4882a593Smuzhiyun <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 44*4882a593Smuzhiyun <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 45*4882a593Smuzhiyun <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 46*4882a593Smuzhiyun <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 47*4882a593Smuzhiyun <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 48*4882a593Smuzhiyun <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 49*4882a593Smuzhiyun <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 50*4882a593Smuzhiyun <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 51*4882a593Smuzhiyun <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 52*4882a593Smuzhiyun <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 53*4882a593Smuzhiyun clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 54*4882a593Smuzhiyun clock-names = "d_audio"; 55*4882a593Smuzhiyun #dma-cells = <1>; 56*4882a593Smuzhiyun}; 57