1*4882a593Smuzhiyun* NVIDIA Tegra APB DMA controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be "nvidia,<chip>-apbdma" 5*4882a593Smuzhiyun- reg: Should contain DMA registers location and length. This shuld include 6*4882a593Smuzhiyun all of the per-channel registers. 7*4882a593Smuzhiyun- interrupts: Should contain all of the per-channel DMA interrupts. 8*4882a593Smuzhiyun- clocks: Must contain one entry, for the module clock. 9*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 10*4882a593Smuzhiyun- resets : Must contain an entry for each entry in reset-names. 11*4882a593Smuzhiyun See ../reset/reset.txt for details. 12*4882a593Smuzhiyun- reset-names : Must include the following entries: 13*4882a593Smuzhiyun - dma 14*4882a593Smuzhiyun- #dma-cells : Must be <1>. This dictates the length of DMA specifiers in 15*4882a593Smuzhiyun client nodes' dmas properties. The specifier represents the DMA request 16*4882a593Smuzhiyun select value for the peripheral. For more details, consult the Tegra TRM's 17*4882a593Smuzhiyun documentation of the APB DMA channel control register REQ_SEL field. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExamples: 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunapbdma: dma@6000a000 { 22*4882a593Smuzhiyun compatible = "nvidia,tegra20-apbdma"; 23*4882a593Smuzhiyun reg = <0x6000a000 0x1200>; 24*4882a593Smuzhiyun interrupts = < 0 136 0x04 25*4882a593Smuzhiyun 0 137 0x04 26*4882a593Smuzhiyun 0 138 0x04 27*4882a593Smuzhiyun 0 139 0x04 28*4882a593Smuzhiyun 0 140 0x04 29*4882a593Smuzhiyun 0 141 0x04 30*4882a593Smuzhiyun 0 142 0x04 31*4882a593Smuzhiyun 0 143 0x04 32*4882a593Smuzhiyun 0 144 0x04 33*4882a593Smuzhiyun 0 145 0x04 34*4882a593Smuzhiyun 0 146 0x04 35*4882a593Smuzhiyun 0 147 0x04 36*4882a593Smuzhiyun 0 148 0x04 37*4882a593Smuzhiyun 0 149 0x04 38*4882a593Smuzhiyun 0 150 0x04 39*4882a593Smuzhiyun 0 151 0x04 >; 40*4882a593Smuzhiyun clocks = <&tegra_car 34>; 41*4882a593Smuzhiyun resets = <&tegra_car 34>; 42*4882a593Smuzhiyun reset-names = "dma"; 43*4882a593Smuzhiyun #dma-cells = <1>; 44*4882a593Smuzhiyun}; 45