1*4882a593Smuzhiyun* Marvell XOR engines 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be one of the following: 5*4882a593Smuzhiyun - "marvell,orion-xor" 6*4882a593Smuzhiyun - "marvell,armada-380-xor" 7*4882a593Smuzhiyun - "marvell,armada-3700-xor". 8*4882a593Smuzhiyun- reg: Should contain registers location and length (two sets) 9*4882a593Smuzhiyun the first set is the low registers, the second set the high 10*4882a593Smuzhiyun registers for the XOR engine. 11*4882a593Smuzhiyun- clocks: pointer to the reference clock 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunThe DT node must also contains sub-nodes for each XOR channel that the 14*4882a593SmuzhiyunXOR engine has. Those sub-nodes have the following required 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun- interrupts: interrupt of the XOR channel 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunThe sub-nodes used to contain one or several of the following 19*4882a593Smuzhiyunproperties, but they are now deprecated: 20*4882a593Smuzhiyun- dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations 21*4882a593Smuzhiyun- dmacap,memset to indicate that the XOR channel is capable of memset operations 22*4882a593Smuzhiyun- dmacap,xor to indicate that the XOR channel is capable of xor operations 23*4882a593Smuzhiyun- dmacap,interrupt to indicate that the XOR channel is capable of 24*4882a593Smuzhiyun generating interrupts 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunExample: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyunxor@d0060900 { 29*4882a593Smuzhiyun compatible = "marvell,orion-xor"; 30*4882a593Smuzhiyun reg = <0xd0060900 0x100 31*4882a593Smuzhiyun 0xd0060b00 0x100>; 32*4882a593Smuzhiyun clocks = <&coreclk 0>; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun xor00 { 35*4882a593Smuzhiyun interrupts = <51>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun xor01 { 38*4882a593Smuzhiyun interrupts = <52>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun}; 41