1*4882a593Smuzhiyun* Mediatek UART APDMA Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible should contain: 5*4882a593Smuzhiyun * "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA 6*4882a593Smuzhiyun * "mediatek,mt6577-uart-dma" for MT6577 and all of the above 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- reg: The base address of the APDMA register bank. 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun- interrupts: A single interrupt specifier. 11*4882a593Smuzhiyun One interrupt per dma-requests, or 8 if no dma-requests property is present 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun- dma-requests: The number of DMA channels 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- clocks : Must contain an entry for each entry in clock-names. 16*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 17*4882a593Smuzhiyun- clock-names: The APDMA clock for register accesses 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun- mediatek,dma-33bits: Present if the DMA requires support 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunExamples: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun apdma: dma-controller@11000400 { 24*4882a593Smuzhiyun compatible = "mediatek,mt2712-uart-dma", 25*4882a593Smuzhiyun "mediatek,mt6577-uart-dma"; 26*4882a593Smuzhiyun reg = <0 0x11000400 0 0x80>, 27*4882a593Smuzhiyun <0 0x11000480 0 0x80>, 28*4882a593Smuzhiyun <0 0x11000500 0 0x80>, 29*4882a593Smuzhiyun <0 0x11000580 0 0x80>, 30*4882a593Smuzhiyun <0 0x11000600 0 0x80>, 31*4882a593Smuzhiyun <0 0x11000680 0 0x80>, 32*4882a593Smuzhiyun <0 0x11000700 0 0x80>, 33*4882a593Smuzhiyun <0 0x11000780 0 0x80>, 34*4882a593Smuzhiyun <0 0x11000800 0 0x80>, 35*4882a593Smuzhiyun <0 0x11000880 0 0x80>, 36*4882a593Smuzhiyun <0 0x11000900 0 0x80>, 37*4882a593Smuzhiyun <0 0x11000980 0 0x80>; 38*4882a593Smuzhiyun interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>, 39*4882a593Smuzhiyun <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, 40*4882a593Smuzhiyun <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>, 41*4882a593Smuzhiyun <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>, 42*4882a593Smuzhiyun <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>, 43*4882a593Smuzhiyun <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>, 44*4882a593Smuzhiyun <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>, 45*4882a593Smuzhiyun <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>, 46*4882a593Smuzhiyun <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>, 47*4882a593Smuzhiyun <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>, 48*4882a593Smuzhiyun <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>, 49*4882a593Smuzhiyun <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>; 50*4882a593Smuzhiyun dma-requests = <12>; 51*4882a593Smuzhiyun clocks = <&pericfg CLK_PERI_AP_DMA>; 52*4882a593Smuzhiyun clock-names = "apdma"; 53*4882a593Smuzhiyun mediatek,dma-33bits; 54*4882a593Smuzhiyun #dma-cells = <1>; 55*4882a593Smuzhiyun }; 56