1*4882a593SmuzhiyunMOXA ART DMA Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunSee dma.txt first 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun- compatible : Must be "moxa,moxart-dma" 8*4882a593Smuzhiyun- reg : Should contain registers location and length 9*4882a593Smuzhiyun- interrupts : Should contain an interrupt-specifier for the sole 10*4882a593Smuzhiyun interrupt generated by the device 11*4882a593Smuzhiyun- #dma-cells : Should be 1, a single cell holding a line request number 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunExample: 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun dma: dma@90500000 { 16*4882a593Smuzhiyun compatible = "moxa,moxart-dma"; 17*4882a593Smuzhiyun reg = <0x90500080 0x40>; 18*4882a593Smuzhiyun interrupts = <24 0>; 19*4882a593Smuzhiyun #dma-cells = <1>; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunClients: 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunDMA clients connected to the MOXA ART DMA controller must use the format 26*4882a593Smuzhiyundescribed in the dma.txt file, using a two-cell specifier for each channel: 27*4882a593Smuzhiyuna phandle plus one integer cells. 28*4882a593SmuzhiyunThe two cells in order are: 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun1. A phandle pointing to the DMA controller. 31*4882a593Smuzhiyun2. Peripheral identifier for the hardware handshaking interface. 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunExample: 34*4882a593SmuzhiyunUse specific request line passing from dma 35*4882a593SmuzhiyunFor example, MMC request line is 5 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun mmc: mmc@98e00000 { 38*4882a593Smuzhiyun compatible = "moxa,moxart-mmc"; 39*4882a593Smuzhiyun reg = <0x98e00000 0x5C>; 40*4882a593Smuzhiyun interrupts = <5 0>; 41*4882a593Smuzhiyun clocks = <&clk_apb>; 42*4882a593Smuzhiyun dmas = <&dma 5>, 43*4882a593Smuzhiyun <&dma 5>; 44*4882a593Smuzhiyun dma-names = "tx", "rx"; 45*4882a593Smuzhiyun }; 46