1*4882a593Smuzhiyun* Milbeaut AXI DMA Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunMilbeaut AXI DMA controller has only memory to memory transfer capability. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun* DMA controller 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired property: 8*4882a593Smuzhiyun- compatible: Should be "socionext,milbeaut-m10v-xdmac" 9*4882a593Smuzhiyun- reg: Should contain DMA registers location and length. 10*4882a593Smuzhiyun- interrupts: Should contain all of the per-channel DMA interrupts. 11*4882a593Smuzhiyun Number of channels is configurable - 2, 4 or 8, so 12*4882a593Smuzhiyun the number of interrupts specified should be {2,4,8}. 13*4882a593Smuzhiyun- #dma-cells: Should be 1. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunExample: 16*4882a593Smuzhiyun xdmac0: dma-controller@1c250000 { 17*4882a593Smuzhiyun compatible = "socionext,milbeaut-m10v-xdmac"; 18*4882a593Smuzhiyun reg = <0x1c250000 0x1000>; 19*4882a593Smuzhiyun interrupts = <0 17 0x4>, 20*4882a593Smuzhiyun <0 18 0x4>, 21*4882a593Smuzhiyun <0 19 0x4>, 22*4882a593Smuzhiyun <0 20 0x4>; 23*4882a593Smuzhiyun #dma-cells = <1>; 24*4882a593Smuzhiyun }; 25