1*4882a593Smuzhiyun* Milbeaut AHB DMA Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunMilbeaut AHB DMA controller has transfer capability below. 4*4882a593Smuzhiyun - device to memory transfer 5*4882a593Smuzhiyun - memory to device transfer 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired property: 8*4882a593Smuzhiyun- compatible: Should be "socionext,milbeaut-m10v-hdmac" 9*4882a593Smuzhiyun- reg: Should contain DMA registers location and length. 10*4882a593Smuzhiyun- interrupts: Should contain all of the per-channel DMA interrupts. 11*4882a593Smuzhiyun Number of channels is configurable - 2, 4 or 8, so 12*4882a593Smuzhiyun the number of interrupts specified should be {2,4,8}. 13*4882a593Smuzhiyun- #dma-cells: Should be 1. Specify the ID of the slave. 14*4882a593Smuzhiyun- clocks: Phandle to the clock used by the HDMAC module. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun hdmac1: dma-controller@1e110000 { 20*4882a593Smuzhiyun compatible = "socionext,milbeaut-m10v-hdmac"; 21*4882a593Smuzhiyun reg = <0x1e110000 0x10000>; 22*4882a593Smuzhiyun interrupts = <0 132 4>, 23*4882a593Smuzhiyun <0 133 4>, 24*4882a593Smuzhiyun <0 134 4>, 25*4882a593Smuzhiyun <0 135 4>, 26*4882a593Smuzhiyun <0 136 4>, 27*4882a593Smuzhiyun <0 137 4>, 28*4882a593Smuzhiyun <0 138 4>, 29*4882a593Smuzhiyun <0 139 4>; 30*4882a593Smuzhiyun #dma-cells = <1>; 31*4882a593Smuzhiyun clocks = <&dummy_clk>; 32*4882a593Smuzhiyun }; 33