1*4882a593SmuzhiyunNXP LPC18xx/43xx DMA MUX (DMA request router) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: "nxp,lpc1850-dmamux" 5*4882a593Smuzhiyun- reg: Memory map for accessing module 6*4882a593Smuzhiyun- #dma-cells: Should be set to <3>. 7*4882a593Smuzhiyun * 1st cell contain the master dma request signal 8*4882a593Smuzhiyun * 2nd cell contain the mux value (0-3) for the peripheral 9*4882a593Smuzhiyun * 3rd cell contain either 1 or 2 depending on the AHB 10*4882a593Smuzhiyun master used. 11*4882a593Smuzhiyun- dma-requests: Number of DMA requests for the mux 12*4882a593Smuzhiyun- dma-masters: phandle pointing to the DMA controller 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunThe DMA controller node need to have the following poroperties: 15*4882a593Smuzhiyun- dma-requests: Number of DMA requests the controller can handle 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyundmac: dma@40002000 { 20*4882a593Smuzhiyun compatible = "nxp,lpc1850-gpdma", "arm,pl080", "arm,primecell"; 21*4882a593Smuzhiyun arm,primecell-periphid = <0x00041080>; 22*4882a593Smuzhiyun reg = <0x40002000 0x1000>; 23*4882a593Smuzhiyun interrupts = <2>; 24*4882a593Smuzhiyun clocks = <&ccu1 CLK_CPU_DMA>; 25*4882a593Smuzhiyun clock-names = "apb_pclk"; 26*4882a593Smuzhiyun #dma-cells = <2>; 27*4882a593Smuzhiyun dma-channels = <8>; 28*4882a593Smuzhiyun dma-requests = <16>; 29*4882a593Smuzhiyun lli-bus-interface-ahb1; 30*4882a593Smuzhiyun lli-bus-interface-ahb2; 31*4882a593Smuzhiyun mem-bus-interface-ahb1; 32*4882a593Smuzhiyun mem-bus-interface-ahb2; 33*4882a593Smuzhiyun memcpy-burst-size = <256>; 34*4882a593Smuzhiyun memcpy-bus-width = <32>; 35*4882a593Smuzhiyun}; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyundmamux: dma-mux { 38*4882a593Smuzhiyun compatible = "nxp,lpc1850-dmamux"; 39*4882a593Smuzhiyun #dma-cells = <3>; 40*4882a593Smuzhiyun dma-requests = <64>; 41*4882a593Smuzhiyun dma-masters = <&dmac>; 42*4882a593Smuzhiyun}; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyunuart0: serial@40081000 { 45*4882a593Smuzhiyun compatible = "nxp,lpc1850-uart", "ns16550a"; 46*4882a593Smuzhiyun reg = <0x40081000 0x1000>; 47*4882a593Smuzhiyun reg-shift = <2>; 48*4882a593Smuzhiyun interrupts = <24>; 49*4882a593Smuzhiyun clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; 50*4882a593Smuzhiyun clock-names = "uartclk", "reg"; 51*4882a593Smuzhiyun dmas = <&dmamux 1 1 2 52*4882a593Smuzhiyun &dmamux 2 1 2>; 53*4882a593Smuzhiyun dma-names = "tx", "rx"; 54*4882a593Smuzhiyun}; 55