1*4882a593Smuzhiyun* Hisilicon K3 DMA controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunSee dma.txt first 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun- compatible: Must be one of 7*4882a593Smuzhiyun- "hisilicon,k3-dma-1.0" 8*4882a593Smuzhiyun- "hisilicon,hisi-pcm-asp-dma-1.0" 9*4882a593Smuzhiyun- reg: Should contain DMA registers location and length. 10*4882a593Smuzhiyun- interrupts: Should contain one interrupt shared by all channel 11*4882a593Smuzhiyun- #dma-cells: see dma.txt, should be 1, para number 12*4882a593Smuzhiyun- dma-channels: physical channels supported 13*4882a593Smuzhiyun- dma-requests: virtual channels supported, each virtual channel 14*4882a593Smuzhiyun have specific request line 15*4882a593Smuzhiyun- clocks: clock required 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunController: 20*4882a593Smuzhiyun dma0: dma@fcd02000 { 21*4882a593Smuzhiyun compatible = "hisilicon,k3-dma-1.0"; 22*4882a593Smuzhiyun reg = <0xfcd02000 0x1000>; 23*4882a593Smuzhiyun #dma-cells = <1>; 24*4882a593Smuzhiyun dma-channels = <16>; 25*4882a593Smuzhiyun dma-requests = <27>; 26*4882a593Smuzhiyun interrupts = <0 12 4>; 27*4882a593Smuzhiyun clocks = <&pclk>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunClient: 31*4882a593SmuzhiyunUse specific request line passing from dmax 32*4882a593SmuzhiyunFor example, i2c0 read channel request line is 18, while write channel use 19 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun i2c0: i2c@fcb08000 { 35*4882a593Smuzhiyun compatible = "snps,designware-i2c"; 36*4882a593Smuzhiyun dmas = <&dma0 18 /* read channel */ 37*4882a593Smuzhiyun &dma0 19>; /* write channel */ 38*4882a593Smuzhiyun dma-names = "rx", "tx"; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun i2c1: i2c@fcb09000 { 42*4882a593Smuzhiyun compatible = "snps,designware-i2c"; 43*4882a593Smuzhiyun dmas = <&dma0 20 /* read channel */ 44*4882a593Smuzhiyun &dma0 21>; /* write channel */ 45*4882a593Smuzhiyun dma-names = "rx", "tx"; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48