1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/dma/ingenic,dma.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Ingenic SoCs DMA Controller DT bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Paul Cercueil <paul@crapouillou.net> 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunallOf: 13*4882a593Smuzhiyun - $ref: "dma-controller.yaml#" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun enum: 18*4882a593Smuzhiyun - ingenic,jz4740-dma 19*4882a593Smuzhiyun - ingenic,jz4725b-dma 20*4882a593Smuzhiyun - ingenic,jz4770-dma 21*4882a593Smuzhiyun - ingenic,jz4780-dma 22*4882a593Smuzhiyun - ingenic,x1000-dma 23*4882a593Smuzhiyun - ingenic,x1830-dma 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun reg: 26*4882a593Smuzhiyun items: 27*4882a593Smuzhiyun - description: Channel-specific registers 28*4882a593Smuzhiyun - description: System control registers 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun interrupts: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun clocks: 34*4882a593Smuzhiyun maxItems: 1 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun "#dma-cells": 37*4882a593Smuzhiyun const: 2 38*4882a593Smuzhiyun description: > 39*4882a593Smuzhiyun DMA clients must use the format described in dma.txt, giving a phandle 40*4882a593Smuzhiyun to the DMA controller plus the following 2 integer cells: 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun - Request type: The DMA request type for transfers to/from the 43*4882a593Smuzhiyun device on the allocated channel, as defined in the SoC documentation. 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun - Channel: If set to 0xffffffff, any available channel will be allocated 46*4882a593Smuzhiyun for the client. Otherwise, the exact channel specified will be used. 47*4882a593Smuzhiyun The channel should be reserved on the DMA controller using the 48*4882a593Smuzhiyun ingenic,reserved-channels property. 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun ingenic,reserved-channels: 51*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/uint32 52*4882a593Smuzhiyun description: > 53*4882a593Smuzhiyun Bitmask of channels to reserve for devices that need a specific 54*4882a593Smuzhiyun channel. These channels will only be assigned when explicitely 55*4882a593Smuzhiyun requested by a client. The primary use for this is channels 0 and 56*4882a593Smuzhiyun 1, which can be configured to have special behaviour for NAND/BCH 57*4882a593Smuzhiyun when using programmable firmware. 58*4882a593Smuzhiyun 59*4882a593Smuzhiyunrequired: 60*4882a593Smuzhiyun - compatible 61*4882a593Smuzhiyun - reg 62*4882a593Smuzhiyun - interrupts 63*4882a593Smuzhiyun - clocks 64*4882a593Smuzhiyun 65*4882a593SmuzhiyununevaluatedProperties: false 66*4882a593Smuzhiyun 67*4882a593Smuzhiyunexamples: 68*4882a593Smuzhiyun - | 69*4882a593Smuzhiyun #include <dt-bindings/clock/jz4780-cgu.h> 70*4882a593Smuzhiyun dma: dma-controller@13420000 { 71*4882a593Smuzhiyun compatible = "ingenic,jz4780-dma"; 72*4882a593Smuzhiyun reg = <0x13420000 0x400>, <0x13421000 0x40>; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun interrupt-parent = <&intc>; 75*4882a593Smuzhiyun interrupts = <10>; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun clocks = <&cgu JZ4780_CLK_PDMA>; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #dma-cells = <2>; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun ingenic,reserved-channels = <0x3>; 82*4882a593Smuzhiyun }; 83