1*4882a593Smuzhiyun* IMG Multi-threaded DMA Controller (MDC) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Must be "img,pistachio-mdc-dma". 5*4882a593Smuzhiyun- reg: Must contain the base address and length of the MDC registers. 6*4882a593Smuzhiyun- interrupts: Must contain all the per-channel DMA interrupts. 7*4882a593Smuzhiyun- clocks: Must contain an entry for each entry in clock-names. 8*4882a593Smuzhiyun See ../clock/clock-bindings.txt for details. 9*4882a593Smuzhiyun- clock-names: Must include the following entries: 10*4882a593Smuzhiyun - sys: MDC system interface clock. 11*4882a593Smuzhiyun- img,cr-periph: Must contain a phandle to the peripheral control syscon 12*4882a593Smuzhiyun node which contains the DMA request to channel mapping registers. 13*4882a593Smuzhiyun- img,max-burst-multiplier: Must be the maximum supported burst size multiplier. 14*4882a593Smuzhiyun The maximum burst size is this value multiplied by the hardware-reported bus 15*4882a593Smuzhiyun width. 16*4882a593Smuzhiyun- #dma-cells: Must be 3: 17*4882a593Smuzhiyun - The first cell is the peripheral's DMA request line. 18*4882a593Smuzhiyun - The second cell is a bitmap specifying to which channels the DMA request 19*4882a593Smuzhiyun line may be mapped (i.e. bit N set indicates channel N is usable). 20*4882a593Smuzhiyun - The third cell is the thread ID to be used by the channel. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunOptional properties: 23*4882a593Smuzhiyun- dma-channels: Number of supported DMA channels, up to 32. If not specified 24*4882a593Smuzhiyun the number reported by the hardware is used. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunExample: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyunmdc: dma-controller@18143000 { 29*4882a593Smuzhiyun compatible = "img,pistachio-mdc-dma"; 30*4882a593Smuzhiyun reg = <0x18143000 0x1000>; 31*4882a593Smuzhiyun interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>, 32*4882a593Smuzhiyun <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>, 33*4882a593Smuzhiyun <GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>, 34*4882a593Smuzhiyun <GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>, 35*4882a593Smuzhiyun <GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>, 36*4882a593Smuzhiyun <GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>, 37*4882a593Smuzhiyun <GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>, 38*4882a593Smuzhiyun <GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>, 39*4882a593Smuzhiyun <GIC_SHARED 35 IRQ_TYPE_LEVEL_HIGH>, 40*4882a593Smuzhiyun <GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>, 41*4882a593Smuzhiyun <GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>, 42*4882a593Smuzhiyun <GIC_SHARED 38 IRQ_TYPE_LEVEL_HIGH>; 43*4882a593Smuzhiyun clocks = <&system_clk>; 44*4882a593Smuzhiyun clock-names = "sys"; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun img,max-burst-multiplier = <16>; 47*4882a593Smuzhiyun img,cr-periph = <&cr_periph>; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #dma-cells = <3>; 50*4882a593Smuzhiyun}; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyunspi@18100f00 { 53*4882a593Smuzhiyun ... 54*4882a593Smuzhiyun dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>; 55*4882a593Smuzhiyun dma-names = "tx", "rx"; 56*4882a593Smuzhiyun ... 57*4882a593Smuzhiyun}; 58