1*4882a593Smuzhiyun* BCM2835 DMA controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe BCM2835 DMA controller has 16 channels in total. 4*4882a593SmuzhiyunOnly the lower 13 channels have an associated IRQ. 5*4882a593SmuzhiyunSome arbitrary channels are used by the firmware 6*4882a593Smuzhiyun(1,3,6,7 in the current firmware version). 7*4882a593SmuzhiyunThe channels 0,2 and 3 have special functionality 8*4882a593Smuzhiyunand should not be used by the driver. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties: 11*4882a593Smuzhiyun- compatible: Should be "brcm,bcm2835-dma". 12*4882a593Smuzhiyun- reg: Should contain DMA registers location and length. 13*4882a593Smuzhiyun- interrupts: Should contain the DMA interrupts associated 14*4882a593Smuzhiyun to the DMA channels in ascending order. 15*4882a593Smuzhiyun- interrupt-names: Should contain the names of the interrupt 16*4882a593Smuzhiyun in the form "dmaXX". 17*4882a593Smuzhiyun Use "dma-shared-all" for the common interrupt line 18*4882a593Smuzhiyun that is shared by all dma channels. 19*4882a593Smuzhiyun- #dma-cells: Must be <1>, the cell in the dmas property of the 20*4882a593Smuzhiyun client device represents the DREQ number. 21*4882a593Smuzhiyun- brcm,dma-channel-mask: Bit mask representing the channels 22*4882a593Smuzhiyun not used by the firmware in ascending order, 23*4882a593Smuzhiyun i.e. first channel corresponds to LSB. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyundma: dma@7e007000 { 28*4882a593Smuzhiyun compatible = "brcm,bcm2835-dma"; 29*4882a593Smuzhiyun reg = <0x7e007000 0xf00>; 30*4882a593Smuzhiyun interrupts = <1 16>, 31*4882a593Smuzhiyun <1 17>, 32*4882a593Smuzhiyun <1 18>, 33*4882a593Smuzhiyun <1 19>, 34*4882a593Smuzhiyun <1 20>, 35*4882a593Smuzhiyun <1 21>, 36*4882a593Smuzhiyun <1 22>, 37*4882a593Smuzhiyun <1 23>, 38*4882a593Smuzhiyun <1 24>, 39*4882a593Smuzhiyun <1 25>, 40*4882a593Smuzhiyun <1 26>, 41*4882a593Smuzhiyun /* dma channel 11-14 share one irq */ 42*4882a593Smuzhiyun <1 27>, 43*4882a593Smuzhiyun <1 27>, 44*4882a593Smuzhiyun <1 27>, 45*4882a593Smuzhiyun <1 27>, 46*4882a593Smuzhiyun /* unused shared irq for all channels */ 47*4882a593Smuzhiyun <1 28>; 48*4882a593Smuzhiyun interrupt-names = "dma0", 49*4882a593Smuzhiyun "dma1", 50*4882a593Smuzhiyun "dma2", 51*4882a593Smuzhiyun "dma3", 52*4882a593Smuzhiyun "dma4", 53*4882a593Smuzhiyun "dma5", 54*4882a593Smuzhiyun "dma6", 55*4882a593Smuzhiyun "dma7", 56*4882a593Smuzhiyun "dma8", 57*4882a593Smuzhiyun "dma9", 58*4882a593Smuzhiyun "dma10", 59*4882a593Smuzhiyun "dma11", 60*4882a593Smuzhiyun "dma12", 61*4882a593Smuzhiyun "dma13", 62*4882a593Smuzhiyun "dma14", 63*4882a593Smuzhiyun "dma-shared-all"; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #dma-cells = <1>; 66*4882a593Smuzhiyun brcm,dma-channel-mask = <0x7f35>; 67*4882a593Smuzhiyun}; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun 70*4882a593SmuzhiyunDMA clients connected to the BCM2835 DMA controller must use the format 71*4882a593Smuzhiyundescribed in the dma.txt file, using a two-cell specifier for each channel. 72*4882a593Smuzhiyun 73*4882a593SmuzhiyunExample: 74*4882a593Smuzhiyun 75*4882a593Smuzhiyunbcm2835_i2s: i2s@7e203000 { 76*4882a593Smuzhiyun compatible = "brcm,bcm2835-i2s"; 77*4882a593Smuzhiyun reg = < 0x7e203000 0x24>; 78*4882a593Smuzhiyun clocks = <&clocks BCM2835_CLOCK_PCM>; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun dmas = <&dma 2>, 81*4882a593Smuzhiyun <&dma 3>; 82*4882a593Smuzhiyun dma-names = "tx", "rx"; 83*4882a593Smuzhiyun}; 84