1*4882a593SmuzhiyunApplied Micro X-Gene SoC DMA nodes 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunDMA nodes are defined to describe on-chip DMA interfaces in 4*4882a593SmuzhiyunAPM X-Gene SoC. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties for DMA interfaces: 7*4882a593Smuzhiyun- compatible: Should be "apm,xgene-dma". 8*4882a593Smuzhiyun- device_type: set to "dma". 9*4882a593Smuzhiyun- reg: Address and length of the register set for the device. 10*4882a593Smuzhiyun It contains the information of registers in the following order: 11*4882a593Smuzhiyun 1st - DMA control and status register address space. 12*4882a593Smuzhiyun 2nd - Descriptor ring control and status register address space. 13*4882a593Smuzhiyun 3rd - Descriptor ring command register address space. 14*4882a593Smuzhiyun 4th - Soc efuse register address space. 15*4882a593Smuzhiyun- interrupts: DMA has 5 interrupts sources. 1st interrupt is 16*4882a593Smuzhiyun DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts 17*4882a593Smuzhiyun are completion interrupts for each DMA channels. 18*4882a593Smuzhiyun- clocks: Reference to the clock entry. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunOptional properties: 21*4882a593Smuzhiyun- dma-coherent : Present if dma operations are coherent 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample: 24*4882a593Smuzhiyun dmaclk: dmaclk@1f27c000 { 25*4882a593Smuzhiyun compatible = "apm,xgene-device-clock"; 26*4882a593Smuzhiyun #clock-cells = <1>; 27*4882a593Smuzhiyun clocks = <&socplldiv2 0>; 28*4882a593Smuzhiyun reg = <0x0 0x1f27c000 0x0 0x1000>; 29*4882a593Smuzhiyun reg-names = "csr-reg"; 30*4882a593Smuzhiyun clock-output-names = "dmaclk"; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun dma: dma@1f270000 { 34*4882a593Smuzhiyun compatible = "apm,xgene-storm-dma"; 35*4882a593Smuzhiyun device_type = "dma"; 36*4882a593Smuzhiyun reg = <0x0 0x1f270000 0x0 0x10000>, 37*4882a593Smuzhiyun <0x0 0x1f200000 0x0 0x10000>, 38*4882a593Smuzhiyun <0x0 0x1b000000 0x0 0x400000>, 39*4882a593Smuzhiyun <0x0 0x1054a000 0x0 0x100>; 40*4882a593Smuzhiyun interrupts = <0x0 0x82 0x4>, 41*4882a593Smuzhiyun <0x0 0xb8 0x4>, 42*4882a593Smuzhiyun <0x0 0xb9 0x4>, 43*4882a593Smuzhiyun <0x0 0xba 0x4>, 44*4882a593Smuzhiyun <0x0 0xbb 0x4>; 45*4882a593Smuzhiyun dma-coherent; 46*4882a593Smuzhiyun clocks = <&dmaclk 0>; 47*4882a593Smuzhiyun }; 48