1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/dma/allwinner,sun6i-a31-dma.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner A31 DMA Controller Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Chen-Yu Tsai <wens@csie.org> 11*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunallOf: 14*4882a593Smuzhiyun - $ref: "dma-controller.yaml#" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun "#dma-cells": 18*4882a593Smuzhiyun const: 1 19*4882a593Smuzhiyun description: The cell is the request line number. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun compatible: 22*4882a593Smuzhiyun oneOf: 23*4882a593Smuzhiyun - const: allwinner,sun6i-a31-dma 24*4882a593Smuzhiyun - const: allwinner,sun8i-a23-dma 25*4882a593Smuzhiyun - const: allwinner,sun8i-a83t-dma 26*4882a593Smuzhiyun - const: allwinner,sun8i-h3-dma 27*4882a593Smuzhiyun - const: allwinner,sun8i-v3s-dma 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun reg: 30*4882a593Smuzhiyun maxItems: 1 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun interrupts: 33*4882a593Smuzhiyun maxItems: 1 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun clocks: 36*4882a593Smuzhiyun maxItems: 1 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun resets: 39*4882a593Smuzhiyun maxItems: 1 40*4882a593Smuzhiyun 41*4882a593Smuzhiyunrequired: 42*4882a593Smuzhiyun - "#dma-cells" 43*4882a593Smuzhiyun - compatible 44*4882a593Smuzhiyun - reg 45*4882a593Smuzhiyun - interrupts 46*4882a593Smuzhiyun - clocks 47*4882a593Smuzhiyun - resets 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunadditionalProperties: false 50*4882a593Smuzhiyun 51*4882a593Smuzhiyunexamples: 52*4882a593Smuzhiyun - | 53*4882a593Smuzhiyun dma: dma-controller@1c02000 { 54*4882a593Smuzhiyun compatible = "allwinner,sun6i-a31-dma"; 55*4882a593Smuzhiyun reg = <0x01c02000 0x1000>; 56*4882a593Smuzhiyun interrupts = <0 50 4>; 57*4882a593Smuzhiyun clocks = <&ahb1_gates 6>; 58*4882a593Smuzhiyun resets = <&ahb1_rst 6>; 59*4882a593Smuzhiyun #dma-cells = <1>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun... 63