1*4882a593SmuzhiyunAnalog Devices AXI-DMAC DMA controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible: Must be "adi,axi-dmac-1.00.a". 5*4882a593Smuzhiyun - reg: Specification for the controllers memory mapped register map. 6*4882a593Smuzhiyun - interrupts: Specification for the controllers interrupt. 7*4882a593Smuzhiyun - clocks: Phandle and specifier to the controllers AXI interface clock 8*4882a593Smuzhiyun - #dma-cells: Must be 1. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired sub-nodes: 11*4882a593Smuzhiyun - adi,channels: This sub-node must contain a sub-node for each DMA channel. For 12*4882a593Smuzhiyun the channel sub-nodes the following bindings apply. They must match the 13*4882a593Smuzhiyun configuration options of the peripheral as it was instantiated. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunRequired properties for adi,channels sub-node: 16*4882a593Smuzhiyun - #size-cells: Must be 0 17*4882a593Smuzhiyun - #address-cells: Must be 1 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunRequired channel sub-node properties: 20*4882a593Smuzhiyun - reg: Which channel this node refers to. 21*4882a593Smuzhiyun - adi,source-bus-width, 22*4882a593Smuzhiyun adi,destination-bus-width: Width of the source or destination bus in bits. 23*4882a593Smuzhiyun - adi,source-bus-type, 24*4882a593Smuzhiyun adi,destination-bus-type: Type of the source or destination bus. Must be one 25*4882a593Smuzhiyun of the following: 26*4882a593Smuzhiyun 0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface 27*4882a593Smuzhiyun 1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface 28*4882a593Smuzhiyun 2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunDeprecated optional channel properties: 31*4882a593Smuzhiyun - adi,length-width: Width of the DMA transfer length register. 32*4882a593Smuzhiyun - adi,cyclic: Must be set if the channel supports hardware cyclic DMA 33*4882a593Smuzhiyun transfers. 34*4882a593Smuzhiyun - adi,2d: Must be set if the channel supports hardware 2D DMA transfers. 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunDMA clients connected to the AXI-DMAC DMA controller must use the format 37*4882a593Smuzhiyundescribed in the dma.txt file using a one-cell specifier. The value of the 38*4882a593Smuzhiyunspecifier refers to the DMA channel index. 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunExample: 41*4882a593Smuzhiyun 42*4882a593Smuzhiyundma: dma@7c420000 { 43*4882a593Smuzhiyun compatible = "adi,axi-dmac-1.00.a"; 44*4882a593Smuzhiyun reg = <0x7c420000 0x10000>; 45*4882a593Smuzhiyun interrupts = <0 57 0>; 46*4882a593Smuzhiyun clocks = <&clkc 16>; 47*4882a593Smuzhiyun #dma-cells = <1>; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun adi,channels { 50*4882a593Smuzhiyun #size-cells = <0>; 51*4882a593Smuzhiyun #address-cells = <1>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun dma-channel@0 { 54*4882a593Smuzhiyun reg = <0>; 55*4882a593Smuzhiyun adi,source-bus-width = <32>; 56*4882a593Smuzhiyun adi,source-bus-type = <ADI_AXI_DMAC_TYPE_MM_AXI>; 57*4882a593Smuzhiyun adi,destination-bus-width = <64>; 58*4882a593Smuzhiyun adi,destination-bus-type = <ADI_AXI_DMAC_TYPE_FIFO>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun}; 62