xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunTexas Instruments OMAP Display Subsystem
2*4882a593Smuzhiyun========================================
3*4882a593Smuzhiyun
4*4882a593SmuzhiyunGeneric Description
5*4882a593Smuzhiyun-------------------
6*4882a593Smuzhiyun
7*4882a593SmuzhiyunThis document is a generic description of the OMAP Display Subsystem bindings.
8*4882a593SmuzhiyunBinding details for each OMAP SoC version are described in respective binding
9*4882a593Smuzhiyundocumentation.
10*4882a593Smuzhiyun
11*4882a593SmuzhiyunThe OMAP Display Subsystem (DSS) hardware consists of DSS Core, DISPC module and
12*4882a593Smuzhiyuna number of encoder modules. All DSS versions contain DSS Core and DISPC, but
13*4882a593Smuzhiyunthe encoder modules vary.
14*4882a593Smuzhiyun
15*4882a593SmuzhiyunThe DSS Core is the parent of the other DSS modules, and manages clock routing,
16*4882a593Smuzhiyunintegration to the SoC, etc.
17*4882a593Smuzhiyun
18*4882a593SmuzhiyunDISPC is the display controller, which reads pixels from the memory and outputs
19*4882a593Smuzhiyuna RGB pixel stream to encoders.
20*4882a593Smuzhiyun
21*4882a593SmuzhiyunThe encoder modules encode the received RGB pixel stream to a video output like
22*4882a593SmuzhiyunHDMI, MIPI DPI, etc.
23*4882a593Smuzhiyun
24*4882a593SmuzhiyunVideo Ports
25*4882a593Smuzhiyun-----------
26*4882a593Smuzhiyun
27*4882a593SmuzhiyunThe DSS Core and the encoders have video port outputs. The structure of the
28*4882a593Smuzhiyunvideo ports is described in Documentation/devicetree/bindings/graph.txt,
29*4882a593Smuzhiyunand the properties for the ports and endpoints for each encoder are
30*4882a593Smuzhiyundescribed in the SoC's DSS binding documentation.
31*4882a593Smuzhiyun
32*4882a593SmuzhiyunThe video ports are used to describe the connections to external hardware, like
33*4882a593Smuzhiyunpanels or external encoders.
34*4882a593Smuzhiyun
35*4882a593SmuzhiyunAliases
36*4882a593Smuzhiyun-------
37*4882a593Smuzhiyun
38*4882a593SmuzhiyunThe board dts file may define aliases for displays to assign "displayX" style
39*4882a593Smuzhiyunname for each display. If no aliases are defined, a semi-random number is used
40*4882a593Smuzhiyunfor the display.
41*4882a593Smuzhiyun
42*4882a593SmuzhiyunExample
43*4882a593Smuzhiyun-------
44*4882a593Smuzhiyun
45*4882a593SmuzhiyunA shortened example of the DSS description for OMAP4, with non-relevant parts
46*4882a593Smuzhiyunremoved, defined in omap4.dtsi:
47*4882a593Smuzhiyun
48*4882a593Smuzhiyundss: dss@58000000 {
49*4882a593Smuzhiyun	compatible = "ti,omap4-dss";
50*4882a593Smuzhiyun	reg = <0x58000000 0x80>;
51*4882a593Smuzhiyun	status = "disabled";
52*4882a593Smuzhiyun	ti,hwmods = "dss_core";
53*4882a593Smuzhiyun	clocks = <&dss_dss_clk>;
54*4882a593Smuzhiyun	clock-names = "fck";
55*4882a593Smuzhiyun	#address-cells = <1>;
56*4882a593Smuzhiyun	#size-cells = <1>;
57*4882a593Smuzhiyun	ranges;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun	dispc@58001000 {
60*4882a593Smuzhiyun		compatible = "ti,omap4-dispc";
61*4882a593Smuzhiyun		reg = <0x58001000 0x1000>;
62*4882a593Smuzhiyun		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
63*4882a593Smuzhiyun		ti,hwmods = "dss_dispc";
64*4882a593Smuzhiyun		clocks = <&dss_dss_clk>;
65*4882a593Smuzhiyun		clock-names = "fck";
66*4882a593Smuzhiyun	};
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun	hdmi: encoder@58006000 {
69*4882a593Smuzhiyun		compatible = "ti,omap4-hdmi";
70*4882a593Smuzhiyun		reg = <0x58006000 0x200>,
71*4882a593Smuzhiyun		      <0x58006200 0x100>,
72*4882a593Smuzhiyun		      <0x58006300 0x100>,
73*4882a593Smuzhiyun		      <0x58006400 0x1000>;
74*4882a593Smuzhiyun		reg-names = "wp", "pll", "phy", "core";
75*4882a593Smuzhiyun		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
76*4882a593Smuzhiyun		status = "disabled";
77*4882a593Smuzhiyun		ti,hwmods = "dss_hdmi";
78*4882a593Smuzhiyun		clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
79*4882a593Smuzhiyun		clock-names = "fck", "sys_clk";
80*4882a593Smuzhiyun	};
81*4882a593Smuzhiyun};
82*4882a593Smuzhiyun
83*4882a593SmuzhiyunA shortened example of the board description for OMAP4 Panda board, defined in
84*4882a593Smuzhiyunomap4-panda.dts.
85*4882a593Smuzhiyun
86*4882a593SmuzhiyunThe Panda board has a DVI and a HDMI connector, and the board contains a TFP410
87*4882a593Smuzhiyunchip (MIPI DPI to DVI encoder) and a TPD12S015 chip (HDMI ESD protection & level
88*4882a593Smuzhiyunshifter). The video pipelines for the connectors are formed as follows:
89*4882a593Smuzhiyun
90*4882a593SmuzhiyunDSS Core --(MIPI DPI)--> TFP410 --(DVI)--> DVI Connector
91*4882a593SmuzhiyunOMAP HDMI --(HDMI)--> TPD12S015 --(HDMI)--> HDMI Connector
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun/ {
94*4882a593Smuzhiyun	aliases {
95*4882a593Smuzhiyun		display0 = &dvi0;
96*4882a593Smuzhiyun		display1 = &hdmi0;
97*4882a593Smuzhiyun	};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun	tfp410: encoder@0 {
100*4882a593Smuzhiyun		compatible = "ti,tfp410";
101*4882a593Smuzhiyun		gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;	/* 0, power-down */
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun		pinctrl-names = "default";
104*4882a593Smuzhiyun		pinctrl-0 = <&tfp410_pins>;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun		ports {
107*4882a593Smuzhiyun			#address-cells = <1>;
108*4882a593Smuzhiyun			#size-cells = <0>;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun			port@0 {
111*4882a593Smuzhiyun				reg = <0>;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun				tfp410_in: endpoint@0 {
114*4882a593Smuzhiyun					remote-endpoint = <&dpi_out>;
115*4882a593Smuzhiyun				};
116*4882a593Smuzhiyun			};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun			port@1 {
119*4882a593Smuzhiyun				reg = <1>;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun				tfp410_out: endpoint@0 {
122*4882a593Smuzhiyun					remote-endpoint = <&dvi_connector_in>;
123*4882a593Smuzhiyun				};
124*4882a593Smuzhiyun			};
125*4882a593Smuzhiyun		};
126*4882a593Smuzhiyun	};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun	dvi0: connector@0 {
129*4882a593Smuzhiyun		compatible = "dvi-connector";
130*4882a593Smuzhiyun		label = "dvi";
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun		i2c-bus = <&i2c3>;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun		port {
135*4882a593Smuzhiyun			dvi_connector_in: endpoint {
136*4882a593Smuzhiyun				remote-endpoint = <&tfp410_out>;
137*4882a593Smuzhiyun			};
138*4882a593Smuzhiyun		};
139*4882a593Smuzhiyun	};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun	tpd12s015: encoder@1 {
142*4882a593Smuzhiyun		compatible = "ti,tpd12s015";
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun		pinctrl-names = "default";
145*4882a593Smuzhiyun		pinctrl-0 = <&tpd12s015_pins>;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun		gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>,	/* 60, CT CP HPD */
148*4882a593Smuzhiyun			<&gpio2 9 GPIO_ACTIVE_HIGH>,	/* 41, LS OE */
149*4882a593Smuzhiyun			<&gpio2 31 GPIO_ACTIVE_HIGH>;	/* 63, HPD */
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun		ports {
152*4882a593Smuzhiyun			#address-cells = <1>;
153*4882a593Smuzhiyun			#size-cells = <0>;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun			port@0 {
156*4882a593Smuzhiyun				reg = <0>;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun				tpd12s015_in: endpoint@0 {
159*4882a593Smuzhiyun					remote-endpoint = <&hdmi_out>;
160*4882a593Smuzhiyun				};
161*4882a593Smuzhiyun			};
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun			port@1 {
164*4882a593Smuzhiyun				reg = <1>;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun				tpd12s015_out: endpoint@0 {
167*4882a593Smuzhiyun					remote-endpoint = <&hdmi_connector_in>;
168*4882a593Smuzhiyun				};
169*4882a593Smuzhiyun			};
170*4882a593Smuzhiyun		};
171*4882a593Smuzhiyun	};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun	hdmi0: connector@1 {
174*4882a593Smuzhiyun		compatible = "hdmi-connector";
175*4882a593Smuzhiyun		label = "hdmi";
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun		port {
178*4882a593Smuzhiyun			hdmi_connector_in: endpoint {
179*4882a593Smuzhiyun				remote-endpoint = <&tpd12s015_out>;
180*4882a593Smuzhiyun			};
181*4882a593Smuzhiyun		};
182*4882a593Smuzhiyun	};
183*4882a593Smuzhiyun};
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun&dss {
186*4882a593Smuzhiyun	status = "ok";
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun	pinctrl-names = "default";
189*4882a593Smuzhiyun	pinctrl-0 = <&dss_dpi_pins>;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun	port {
192*4882a593Smuzhiyun		dpi_out: endpoint {
193*4882a593Smuzhiyun			remote-endpoint = <&tfp410_in>;
194*4882a593Smuzhiyun			data-lines = <24>;
195*4882a593Smuzhiyun		};
196*4882a593Smuzhiyun	};
197*4882a593Smuzhiyun};
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun&hdmi {
200*4882a593Smuzhiyun	status = "ok";
201*4882a593Smuzhiyun	vdda-supply = <&vdac>;
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun	pinctrl-names = "default";
204*4882a593Smuzhiyun	pinctrl-0 = <&dss_hdmi_pins>;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun	port {
207*4882a593Smuzhiyun		hdmi_out: endpoint {
208*4882a593Smuzhiyun			remote-endpoint = <&tpd12s015_in>;
209*4882a593Smuzhiyun		};
210*4882a593Smuzhiyun	};
211*4882a593Smuzhiyun};
212