xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2*4882a593Smuzhiyun# Copyright 2019 Texas Instruments Incorporated
3*4882a593Smuzhiyun%YAML 1.2
4*4882a593Smuzhiyun---
5*4882a593Smuzhiyun$id: "http://devicetree.org/schemas/display/ti/ti,k2g-dss.yaml#"
6*4882a593Smuzhiyun$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7*4882a593Smuzhiyun
8*4882a593Smuzhiyuntitle: Texas Instruments K2G Display Subsystem
9*4882a593Smuzhiyun
10*4882a593Smuzhiyunmaintainers:
11*4882a593Smuzhiyun  - Jyri Sarha <jsarha@ti.com>
12*4882a593Smuzhiyun  - Tomi Valkeinen <tomi.valkeinen@ti.com>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyundescription: |
15*4882a593Smuzhiyun  The K2G DSS is an ultra-light version of TI Keystone Display
16*4882a593Smuzhiyun  SubSystem. It has only one output port and video plane. The
17*4882a593Smuzhiyun  output is DPI.
18*4882a593Smuzhiyun
19*4882a593Smuzhiyunproperties:
20*4882a593Smuzhiyun  compatible:
21*4882a593Smuzhiyun    const: ti,k2g-dss
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun  reg:
24*4882a593Smuzhiyun    items:
25*4882a593Smuzhiyun      - description: cfg DSS top level
26*4882a593Smuzhiyun      - description: common DISPC common
27*4882a593Smuzhiyun      - description: VID1 video plane 1
28*4882a593Smuzhiyun      - description: OVR1 overlay manager for vp1
29*4882a593Smuzhiyun      - description: VP1 video port 1
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun  reg-names:
32*4882a593Smuzhiyun    items:
33*4882a593Smuzhiyun      - const: cfg
34*4882a593Smuzhiyun      - const: common
35*4882a593Smuzhiyun      - const: vid1
36*4882a593Smuzhiyun      - const: ovr1
37*4882a593Smuzhiyun      - const: vp1
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun  clocks:
40*4882a593Smuzhiyun    items:
41*4882a593Smuzhiyun      - description: fck DSS functional clock
42*4882a593Smuzhiyun      - description: vp1 Video Port 1 pixel clock
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun  clock-names:
45*4882a593Smuzhiyun    items:
46*4882a593Smuzhiyun      - const: fck
47*4882a593Smuzhiyun      - const: vp1
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun  interrupts:
50*4882a593Smuzhiyun    maxItems: 1
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun  power-domains:
53*4882a593Smuzhiyun    maxItems: 1
54*4882a593Smuzhiyun    description: phandle to the associated power domain
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun  port:
57*4882a593Smuzhiyun    type: object
58*4882a593Smuzhiyun    description:
59*4882a593Smuzhiyun      Port as described in Documentation/devicetree/bindings/graph.txt.
60*4882a593Smuzhiyun      The DSS DPI output port node
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun  max-memory-bandwidth:
63*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32
64*4882a593Smuzhiyun    description:
65*4882a593Smuzhiyun      Input memory (from main memory to dispc) bandwidth limit in
66*4882a593Smuzhiyun      bytes per second
67*4882a593Smuzhiyun
68*4882a593Smuzhiyunrequired:
69*4882a593Smuzhiyun  - compatible
70*4882a593Smuzhiyun  - reg
71*4882a593Smuzhiyun  - reg-names
72*4882a593Smuzhiyun  - clocks
73*4882a593Smuzhiyun  - clock-names
74*4882a593Smuzhiyun  - interrupts
75*4882a593Smuzhiyun  - port
76*4882a593Smuzhiyun
77*4882a593SmuzhiyunadditionalProperties: false
78*4882a593Smuzhiyun
79*4882a593Smuzhiyunexamples:
80*4882a593Smuzhiyun  - |
81*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
82*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/irq.h>
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun    dss: dss@2540000 {
85*4882a593Smuzhiyun            compatible = "ti,k2g-dss";
86*4882a593Smuzhiyun            reg =   <0x02540000 0x400>,
87*4882a593Smuzhiyun                    <0x02550000 0x1000>,
88*4882a593Smuzhiyun                    <0x02557000 0x1000>,
89*4882a593Smuzhiyun                    <0x0255a800 0x100>,
90*4882a593Smuzhiyun                    <0x0255ac00 0x100>;
91*4882a593Smuzhiyun            reg-names = "cfg", "common", "vid1", "ovr1", "vp1";
92*4882a593Smuzhiyun            clocks =        <&k2g_clks 0x2 0>,
93*4882a593Smuzhiyun                            <&k2g_clks 0x2 1>;
94*4882a593Smuzhiyun            clock-names = "fck", "vp1";
95*4882a593Smuzhiyun            interrupts = <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun            power-domains = <&k2g_pds 0x2>;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun            max-memory-bandwidth = <230000000>;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun            port {
102*4882a593Smuzhiyun                    dpi_out: endpoint {
103*4882a593Smuzhiyun                            remote-endpoint = <&sii9022_in>;
104*4882a593Smuzhiyun                    };
105*4882a593Smuzhiyun            };
106*4882a593Smuzhiyun    };
107