xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2*4882a593Smuzhiyun# Copyright 2019 Texas Instruments Incorporated
3*4882a593Smuzhiyun%YAML 1.2
4*4882a593Smuzhiyun---
5*4882a593Smuzhiyun$id: "http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#"
6*4882a593Smuzhiyun$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7*4882a593Smuzhiyun
8*4882a593Smuzhiyuntitle: Texas Instruments AM65x Display Subsystem
9*4882a593Smuzhiyun
10*4882a593Smuzhiyunmaintainers:
11*4882a593Smuzhiyun  - Jyri Sarha <jsarha@ti.com>
12*4882a593Smuzhiyun  - Tomi Valkeinen <tomi.valkeinen@ti.com>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyundescription: |
15*4882a593Smuzhiyun  The AM65x TI Keystone Display SubSystem with two output ports and
16*4882a593Smuzhiyun  two video planes. The first video port supports OLDI and the second
17*4882a593Smuzhiyun  supports DPI format. The fist plane is full video plane with all
18*4882a593Smuzhiyun  features and the second is a "lite plane" without scaling support.
19*4882a593Smuzhiyun
20*4882a593Smuzhiyunproperties:
21*4882a593Smuzhiyun  compatible:
22*4882a593Smuzhiyun    const: ti,am65x-dss
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun  reg:
25*4882a593Smuzhiyun    description:
26*4882a593Smuzhiyun      Addresses to each DSS memory region described in the SoC's TRM.
27*4882a593Smuzhiyun    items:
28*4882a593Smuzhiyun      - description: common DSS register area
29*4882a593Smuzhiyun      - description: VIDL1 light video plane
30*4882a593Smuzhiyun      - description: VID video plane
31*4882a593Smuzhiyun      - description: OVR1 overlay manager for vp1
32*4882a593Smuzhiyun      - description: OVR2 overlay manager for vp2
33*4882a593Smuzhiyun      - description: VP1 video port 1
34*4882a593Smuzhiyun      - description: VP2 video port 2
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun  reg-names:
37*4882a593Smuzhiyun    items:
38*4882a593Smuzhiyun      - const: common
39*4882a593Smuzhiyun      - const: vidl1
40*4882a593Smuzhiyun      - const: vid
41*4882a593Smuzhiyun      - const: ovr1
42*4882a593Smuzhiyun      - const: ovr2
43*4882a593Smuzhiyun      - const: vp1
44*4882a593Smuzhiyun      - const: vp2
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun  clocks:
47*4882a593Smuzhiyun    items:
48*4882a593Smuzhiyun      - description: fck DSS functional clock
49*4882a593Smuzhiyun      - description: vp1 Video Port 1 pixel clock
50*4882a593Smuzhiyun      - description: vp2 Video Port 2 pixel clock
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun  clock-names:
53*4882a593Smuzhiyun    items:
54*4882a593Smuzhiyun      - const: fck
55*4882a593Smuzhiyun      - const: vp1
56*4882a593Smuzhiyun      - const: vp2
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun  interrupts:
59*4882a593Smuzhiyun    maxItems: 1
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun  power-domains:
62*4882a593Smuzhiyun    maxItems: 1
63*4882a593Smuzhiyun    description: phandle to the associated power domain
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun  ports:
66*4882a593Smuzhiyun    type: object
67*4882a593Smuzhiyun    description:
68*4882a593Smuzhiyun      Ports as described in Documentation/devicetree/bindings/graph.txt
69*4882a593Smuzhiyun    properties:
70*4882a593Smuzhiyun      "#address-cells":
71*4882a593Smuzhiyun        const: 1
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun      "#size-cells":
74*4882a593Smuzhiyun        const: 0
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun      port@0:
77*4882a593Smuzhiyun        type: object
78*4882a593Smuzhiyun        description:
79*4882a593Smuzhiyun          The DSS OLDI output port node form video port 1
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun      port@1:
82*4882a593Smuzhiyun        type: object
83*4882a593Smuzhiyun        description:
84*4882a593Smuzhiyun          The DSS DPI output port node from video port 2
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun    required:
87*4882a593Smuzhiyun      - "#address-cells"
88*4882a593Smuzhiyun      - "#size-cells"
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun  ti,am65x-oldi-io-ctrl:
91*4882a593Smuzhiyun    $ref: "/schemas/types.yaml#/definitions/phandle-array"
92*4882a593Smuzhiyun    maxItems: 1
93*4882a593Smuzhiyun    description:
94*4882a593Smuzhiyun      phandle to syscon device node mapping OLDI IO_CTRL registers.
95*4882a593Smuzhiyun      The mapped range should point to OLDI_DAT0_IO_CTRL, map it and
96*4882a593Smuzhiyun      following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL,
97*4882a593Smuzhiyun      and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI
98*4882a593Smuzhiyun      interface to work.
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun  max-memory-bandwidth:
101*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32
102*4882a593Smuzhiyun    description:
103*4882a593Smuzhiyun      Input memory (from main memory to dispc) bandwidth limit in
104*4882a593Smuzhiyun      bytes per second
105*4882a593Smuzhiyun
106*4882a593Smuzhiyunrequired:
107*4882a593Smuzhiyun  - compatible
108*4882a593Smuzhiyun  - reg
109*4882a593Smuzhiyun  - reg-names
110*4882a593Smuzhiyun  - clocks
111*4882a593Smuzhiyun  - clock-names
112*4882a593Smuzhiyun  - interrupts
113*4882a593Smuzhiyun  - ports
114*4882a593Smuzhiyun
115*4882a593SmuzhiyunadditionalProperties: false
116*4882a593Smuzhiyun
117*4882a593Smuzhiyunexamples:
118*4882a593Smuzhiyun  - |
119*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
120*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/irq.h>
121*4882a593Smuzhiyun    #include <dt-bindings/soc/ti,sci_pm_domain.h>
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun    dss: dss@4a00000 {
124*4882a593Smuzhiyun            compatible = "ti,am65x-dss";
125*4882a593Smuzhiyun            reg =   <0x04a00000 0x1000>, /* common */
126*4882a593Smuzhiyun                    <0x04a02000 0x1000>, /* vidl1 */
127*4882a593Smuzhiyun                    <0x04a06000 0x1000>, /* vid */
128*4882a593Smuzhiyun                    <0x04a07000 0x1000>, /* ovr1 */
129*4882a593Smuzhiyun                    <0x04a08000 0x1000>, /* ovr2 */
130*4882a593Smuzhiyun                    <0x04a0a000 0x1000>, /* vp1 */
131*4882a593Smuzhiyun                    <0x04a0b000 0x1000>; /* vp2 */
132*4882a593Smuzhiyun            reg-names = "common", "vidl1", "vid",
133*4882a593Smuzhiyun                    "ovr1", "ovr2", "vp1", "vp2";
134*4882a593Smuzhiyun            ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
135*4882a593Smuzhiyun            power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
136*4882a593Smuzhiyun            clocks =        <&k3_clks 67 1>,
137*4882a593Smuzhiyun                            <&k3_clks 216 1>,
138*4882a593Smuzhiyun                            <&k3_clks 67 2>;
139*4882a593Smuzhiyun            clock-names = "fck", "vp1", "vp2";
140*4882a593Smuzhiyun            interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
141*4882a593Smuzhiyun            ports {
142*4882a593Smuzhiyun                    #address-cells = <1>;
143*4882a593Smuzhiyun                    #size-cells = <0>;
144*4882a593Smuzhiyun                    port@0 {
145*4882a593Smuzhiyun                            reg = <0>;
146*4882a593Smuzhiyun                            oldi_out0: endpoint {
147*4882a593Smuzhiyun                                    remote-endpoint = <&lcd_in0>;
148*4882a593Smuzhiyun                            };
149*4882a593Smuzhiyun                    };
150*4882a593Smuzhiyun            };
151*4882a593Smuzhiyun    };
152