1*4882a593SmuzhiyunTPD12S015 HDMI level shifter and ESD protection chip 2*4882a593Smuzhiyun==================================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible: "ti,tpd12s015" 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunOptional properties: 8*4882a593Smuzhiyun- gpios: CT CP HPD, LS OE and HPD gpios 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired nodes: 11*4882a593Smuzhiyun- Video port 0 for HDMI input 12*4882a593Smuzhiyun- Video port 1 for HDMI output 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunExample 15*4882a593Smuzhiyun------- 16*4882a593Smuzhiyun 17*4882a593Smuzhiyuntpd12s015: encoder@1 { 18*4882a593Smuzhiyun compatible = "ti,tpd12s015"; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */ 21*4882a593Smuzhiyun <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */ 22*4882a593Smuzhiyun <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun ports { 25*4882a593Smuzhiyun #address-cells = <1>; 26*4882a593Smuzhiyun #size-cells = <0>; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun port@0 { 29*4882a593Smuzhiyun reg = <0>; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun tpd12s015_in: endpoint@0 { 32*4882a593Smuzhiyun remote-endpoint = <&hdmi_out>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun port@1 { 37*4882a593Smuzhiyun reg = <1>; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun tpd12s015_out: endpoint@0 { 40*4882a593Smuzhiyun remote-endpoint = <&hdmi_connector_in>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun}; 45