1*4882a593SmuzhiyunNVIDIA Tegra MIPI pad calibration controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: "nvidia,tegra<chip>-mipi" 5*4882a593Smuzhiyun- reg: Physical base address and length of the controller's registers. 6*4882a593Smuzhiyun- clocks: Must contain an entry for each entry in clock-names. 7*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 8*4882a593Smuzhiyun- clock-names: Must include the following entries: 9*4882a593Smuzhiyun - mipi-cal 10*4882a593Smuzhiyun- #nvidia,mipi-calibrate-cells: Should be 1. The cell is a bitmask of the pads 11*4882a593Smuzhiyun that need to be calibrated for a given device. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunUser nodes need to contain an nvidia,mipi-calibrate property that has a 14*4882a593Smuzhiyunphandle to refer to the calibration controller node and a bitmask of the pads 15*4882a593Smuzhiyunthat need to be calibrated. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun mipi: mipi@700e3000 { 20*4882a593Smuzhiyun compatible = "nvidia,tegra114-mipi"; 21*4882a593Smuzhiyun reg = <0x700e3000 0x100>; 22*4882a593Smuzhiyun clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; 23*4882a593Smuzhiyun clock-names = "mipi-cal"; 24*4882a593Smuzhiyun #nvidia,mipi-calibrate-cells = <1>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun ... 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun host1x@50000000 { 30*4882a593Smuzhiyun ... 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun dsi@54300000 { 33*4882a593Smuzhiyun ... 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun nvidia,mipi-calibrate = <&mipi 0x060>; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun ... 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun ... 41*4882a593Smuzhiyun }; 42