xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/ste,mcde.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunST-Ericsson Multi Channel Display Engine MCDE
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunThe ST-Ericsson MCDE is a display controller with support for compositing
4*4882a593Smuzhiyunand displaying several channels memory resident graphics data on DSI or
5*4882a593SmuzhiyunLCD displays or bridges. It is used in the ST-Ericsson U8500 platform.
6*4882a593Smuzhiyun
7*4882a593SmuzhiyunRequired properties:
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun- compatible: must be:
10*4882a593Smuzhiyun  "ste,mcde"
11*4882a593Smuzhiyun- reg: register base for the main MCDE control registers, should be
12*4882a593Smuzhiyun  0x1000 in size
13*4882a593Smuzhiyun- interrupts: the interrupt line for the MCDE
14*4882a593Smuzhiyun- epod-supply: a phandle to the EPOD regulator
15*4882a593Smuzhiyun- vana-supply: a phandle to the analog voltage regulator
16*4882a593Smuzhiyun- clocks: an array of the MCDE clocks in this strict order:
17*4882a593Smuzhiyun  MCDECLK (main MCDE clock), LCDCLK (LCD clock), PLLDSI
18*4882a593Smuzhiyun  (HDMI clock), DSI0ESCLK (DSI0 energy save clock),
19*4882a593Smuzhiyun  DSI1ESCLK (DSI1 energy save clock), DSI2ESCLK (DSI2 energy
20*4882a593Smuzhiyun  save clock)
21*4882a593Smuzhiyun- clock-names: must be the following array:
22*4882a593Smuzhiyun  "mcde", "lcd", "hdmi"
23*4882a593Smuzhiyun  to match the required clock inputs above.
24*4882a593Smuzhiyun- #address-cells: should be <1> (for the DSI hosts that will be children)
25*4882a593Smuzhiyun- #size-cells: should be <1> (for the DSI hosts that will be children)
26*4882a593Smuzhiyun- ranges: this should always be stated
27*4882a593Smuzhiyun
28*4882a593SmuzhiyunRequired subnodes:
29*4882a593Smuzhiyun
30*4882a593SmuzhiyunThe devicetree must specify subnodes for the DSI host adapters.
31*4882a593SmuzhiyunThese must have the following characteristics:
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun- compatible: must be:
34*4882a593Smuzhiyun  "ste,mcde-dsi"
35*4882a593Smuzhiyun- reg: must specify the register range for the DSI host
36*4882a593Smuzhiyun- vana-supply: phandle to the VANA voltage regulator
37*4882a593Smuzhiyun- clocks: phandles to the high speed and low power (energy save) clocks
38*4882a593Smuzhiyun  the high speed clock is not present on the third (dsi2) block, so it
39*4882a593Smuzhiyun  should only have the "lp" clock
40*4882a593Smuzhiyun- clock-names: "hs" for the high speed clock and "lp" for the low power
41*4882a593Smuzhiyun  (energy save) clock
42*4882a593Smuzhiyun- #address-cells: should be <1>
43*4882a593Smuzhiyun- #size-cells: should be <0>
44*4882a593Smuzhiyun
45*4882a593SmuzhiyunDisplay panels and bridges will appear as children on the DSI hosts, and
46*4882a593Smuzhiyunthe displays are connected to the DSI hosts using the common binding
47*4882a593Smuzhiyunfor video transmitter interfaces; see
48*4882a593SmuzhiyunDocumentation/devicetree/bindings/media/video-interfaces.txt
49*4882a593Smuzhiyun
50*4882a593SmuzhiyunIf a DSI host is unused (not connected) it will have no children defined.
51*4882a593Smuzhiyun
52*4882a593SmuzhiyunExample:
53*4882a593Smuzhiyun
54*4882a593Smuzhiyunmcde@a0350000 {
55*4882a593Smuzhiyun	compatible = "ste,mcde";
56*4882a593Smuzhiyun	reg = <0xa0350000 0x1000>;
57*4882a593Smuzhiyun	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
58*4882a593Smuzhiyun	epod-supply = <&db8500_b2r2_mcde_reg>;
59*4882a593Smuzhiyun	vana-supply = <&ab8500_ldo_ana_reg>;
60*4882a593Smuzhiyun	clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
61*4882a593Smuzhiyun		 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
62*4882a593Smuzhiyun		 <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */
63*4882a593Smuzhiyun	clock-names = "mcde", "lcd", "hdmi";
64*4882a593Smuzhiyun	#address-cells = <1>;
65*4882a593Smuzhiyun	#size-cells = <1>;
66*4882a593Smuzhiyun	ranges;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun	dsi0: dsi@a0351000 {
69*4882a593Smuzhiyun		compatible = "ste,mcde-dsi";
70*4882a593Smuzhiyun		reg = <0xa0351000 0x1000>;
71*4882a593Smuzhiyun		vana-supply = <&ab8500_ldo_ana_reg>;
72*4882a593Smuzhiyun		clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
73*4882a593Smuzhiyun		clock-names = "hs", "lp";
74*4882a593Smuzhiyun		#address-cells = <1>;
75*4882a593Smuzhiyun		#size-cells = <0>;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun		panel {
78*4882a593Smuzhiyun			compatible = "samsung,s6d16d0";
79*4882a593Smuzhiyun			reg = <0>;
80*4882a593Smuzhiyun			vdd1-supply = <&ab8500_ldo_aux1_reg>;
81*4882a593Smuzhiyun			reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
82*4882a593Smuzhiyun		};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun	};
85*4882a593Smuzhiyun	dsi1: dsi@a0352000 {
86*4882a593Smuzhiyun		compatible = "ste,mcde-dsi";
87*4882a593Smuzhiyun		reg = <0xa0352000 0x1000>;
88*4882a593Smuzhiyun		vana-supply = <&ab8500_ldo_ana_reg>;
89*4882a593Smuzhiyun		clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>;
90*4882a593Smuzhiyun		clock-names = "hs", "lp";
91*4882a593Smuzhiyun		#address-cells = <1>;
92*4882a593Smuzhiyun		#size-cells = <0>;
93*4882a593Smuzhiyun	};
94*4882a593Smuzhiyun	dsi2: dsi@a0353000 {
95*4882a593Smuzhiyun		compatible = "ste,mcde-dsi";
96*4882a593Smuzhiyun		reg = <0xa0353000 0x1000>;
97*4882a593Smuzhiyun		vana-supply = <&ab8500_ldo_ana_reg>;
98*4882a593Smuzhiyun		/* This DSI port only has the Low Power / Energy Save clock */
99*4882a593Smuzhiyun		clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>;
100*4882a593Smuzhiyun		clock-names = "lp";
101*4882a593Smuzhiyun		#address-cells = <1>;
102*4882a593Smuzhiyun		#size-cells = <0>;
103*4882a593Smuzhiyun	};
104*4882a593Smuzhiyun};
105