1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/st,stm32-ltdc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: STMicroelectronics STM32 lcd-tft display controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Philippe Cornu <philippe.cornu@st.com> 11*4882a593Smuzhiyun - Yannick Fertre <yannick.fertre@st.com> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunproperties: 14*4882a593Smuzhiyun compatible: 15*4882a593Smuzhiyun const: st,stm32-ltdc 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun reg: 18*4882a593Smuzhiyun maxItems: 1 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun interrupts: 21*4882a593Smuzhiyun items: 22*4882a593Smuzhiyun - description: events interrupt line. 23*4882a593Smuzhiyun - description: errors interrupt line. 24*4882a593Smuzhiyun minItems: 1 25*4882a593Smuzhiyun maxItems: 2 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun clocks: 28*4882a593Smuzhiyun maxItems: 1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun clock-names: 31*4882a593Smuzhiyun items: 32*4882a593Smuzhiyun - const: lcd 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun resets: 35*4882a593Smuzhiyun maxItems: 1 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun port: 38*4882a593Smuzhiyun type: object 39*4882a593Smuzhiyun description: 40*4882a593Smuzhiyun "Video port for DPI RGB output. 41*4882a593Smuzhiyun ltdc has one video port with up to 2 endpoints: 42*4882a593Smuzhiyun - for external dpi rgb panel or bridge, using gpios. 43*4882a593Smuzhiyun - for internal dpi input of the MIPI DSI host controller. 44*4882a593Smuzhiyun Note: These 2 endpoints cannot be activated simultaneously. 45*4882a593Smuzhiyun Please refer to the bindings defined in 46*4882a593Smuzhiyun Documentation/devicetree/bindings/media/video-interfaces.txt." 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunrequired: 49*4882a593Smuzhiyun - compatible 50*4882a593Smuzhiyun - reg 51*4882a593Smuzhiyun - interrupts 52*4882a593Smuzhiyun - clocks 53*4882a593Smuzhiyun - clock-names 54*4882a593Smuzhiyun - resets 55*4882a593Smuzhiyun - port 56*4882a593Smuzhiyun 57*4882a593SmuzhiyunadditionalProperties: false 58*4882a593Smuzhiyun 59*4882a593Smuzhiyunexamples: 60*4882a593Smuzhiyun - | 61*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 62*4882a593Smuzhiyun #include <dt-bindings/clock/stm32mp1-clks.h> 63*4882a593Smuzhiyun #include <dt-bindings/reset/stm32mp1-resets.h> 64*4882a593Smuzhiyun ltdc: display-controller@40016800 { 65*4882a593Smuzhiyun compatible = "st,stm32-ltdc"; 66*4882a593Smuzhiyun reg = <0x5a001000 0x400>; 67*4882a593Smuzhiyun interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 68*4882a593Smuzhiyun <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 69*4882a593Smuzhiyun clocks = <&rcc LTDC_PX>; 70*4882a593Smuzhiyun clock-names = "lcd"; 71*4882a593Smuzhiyun resets = <&rcc LTDC_R>; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun port { 74*4882a593Smuzhiyun ltdc_out_dsi: endpoint { 75*4882a593Smuzhiyun remote-endpoint = <&dsi_in>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun... 81*4882a593Smuzhiyun 82