xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: STMicroelectronics STM32 DSI host controller
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Philippe Cornu <philippe.cornu@st.com>
11*4882a593Smuzhiyun  - Yannick Fertre <yannick.fertre@st.com>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyundescription:
14*4882a593Smuzhiyun  The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
15*4882a593Smuzhiyun
16*4882a593SmuzhiyunallOf:
17*4882a593Smuzhiyun  - $ref: dsi-controller.yaml#
18*4882a593Smuzhiyun
19*4882a593Smuzhiyunproperties:
20*4882a593Smuzhiyun  compatible:
21*4882a593Smuzhiyun    const: st,stm32-dsi
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun  reg:
24*4882a593Smuzhiyun    maxItems: 1
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun  clocks:
27*4882a593Smuzhiyun    items:
28*4882a593Smuzhiyun      - description: Module Clock
29*4882a593Smuzhiyun      - description: DSI bus clock
30*4882a593Smuzhiyun      - description: Pixel clock
31*4882a593Smuzhiyun    minItems: 2
32*4882a593Smuzhiyun    maxItems: 3
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun  clock-names:
35*4882a593Smuzhiyun    items:
36*4882a593Smuzhiyun      - const: pclk
37*4882a593Smuzhiyun      - const: ref
38*4882a593Smuzhiyun      - const: px_clk
39*4882a593Smuzhiyun    minItems: 2
40*4882a593Smuzhiyun    maxItems: 3
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun  resets:
43*4882a593Smuzhiyun    maxItems: 1
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun  reset-names:
46*4882a593Smuzhiyun    items:
47*4882a593Smuzhiyun      - const: apb
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun  phy-dsi-supply:
50*4882a593Smuzhiyun    description:
51*4882a593Smuzhiyun      Phandle of the regulator that provides the supply voltage.
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun  ports:
54*4882a593Smuzhiyun    type: object
55*4882a593Smuzhiyun    description:
56*4882a593Smuzhiyun      A node containing DSI input & output port nodes with endpoint
57*4882a593Smuzhiyun      definitions as documented in
58*4882a593Smuzhiyun      Documentation/devicetree/bindings/media/video-interfaces.txt
59*4882a593Smuzhiyun      Documentation/devicetree/bindings/graph.txt
60*4882a593Smuzhiyun    properties:
61*4882a593Smuzhiyun      port@0:
62*4882a593Smuzhiyun        type: object
63*4882a593Smuzhiyun        description:
64*4882a593Smuzhiyun          DSI input port node, connected to the ltdc rgb output port.
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun      port@1:
67*4882a593Smuzhiyun        type: object
68*4882a593Smuzhiyun        description:
69*4882a593Smuzhiyun          DSI output port node, connected to a panel or a bridge input port"
70*4882a593Smuzhiyun
71*4882a593Smuzhiyunrequired:
72*4882a593Smuzhiyun  - "#address-cells"
73*4882a593Smuzhiyun  - "#size-cells"
74*4882a593Smuzhiyun  - compatible
75*4882a593Smuzhiyun  - reg
76*4882a593Smuzhiyun  - clocks
77*4882a593Smuzhiyun  - clock-names
78*4882a593Smuzhiyun  - ports
79*4882a593Smuzhiyun
80*4882a593SmuzhiyununevaluatedProperties: false
81*4882a593Smuzhiyun
82*4882a593Smuzhiyunexamples:
83*4882a593Smuzhiyun  - |
84*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
85*4882a593Smuzhiyun    #include <dt-bindings/clock/stm32mp1-clks.h>
86*4882a593Smuzhiyun    #include <dt-bindings/reset/stm32mp1-resets.h>
87*4882a593Smuzhiyun    #include <dt-bindings/gpio/gpio.h>
88*4882a593Smuzhiyun    dsi: dsi@5a000000 {
89*4882a593Smuzhiyun        compatible = "st,stm32-dsi";
90*4882a593Smuzhiyun        reg = <0x5a000000 0x800>;
91*4882a593Smuzhiyun        clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
92*4882a593Smuzhiyun        clock-names = "pclk", "ref", "px_clk";
93*4882a593Smuzhiyun        resets = <&rcc DSI_R>;
94*4882a593Smuzhiyun        reset-names = "apb";
95*4882a593Smuzhiyun        phy-dsi-supply = <&reg18>;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun        #address-cells = <1>;
98*4882a593Smuzhiyun        #size-cells = <0>;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun        ports {
101*4882a593Smuzhiyun              #address-cells = <1>;
102*4882a593Smuzhiyun              #size-cells = <0>;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun              port@0 {
105*4882a593Smuzhiyun                    reg = <0>;
106*4882a593Smuzhiyun                    dsi_in: endpoint {
107*4882a593Smuzhiyun                        remote-endpoint = <&ltdc_ep1_out>;
108*4882a593Smuzhiyun                    };
109*4882a593Smuzhiyun              };
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun              port@1 {
112*4882a593Smuzhiyun                    reg = <1>;
113*4882a593Smuzhiyun                    dsi_out: endpoint {
114*4882a593Smuzhiyun                        remote-endpoint = <&panel_in>;
115*4882a593Smuzhiyun                    };
116*4882a593Smuzhiyun              };
117*4882a593Smuzhiyun        };
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun        panel-dsi@0 {
120*4882a593Smuzhiyun              compatible = "orisetech,otm8009a";
121*4882a593Smuzhiyun              reg = <0>;
122*4882a593Smuzhiyun              reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
123*4882a593Smuzhiyun              power-supply = <&v3v3>;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun              port {
126*4882a593Smuzhiyun                    panel_in: endpoint {
127*4882a593Smuzhiyun                        remote-endpoint = <&dsi_out>;
128*4882a593Smuzhiyun                    };
129*4882a593Smuzhiyun              };
130*4882a593Smuzhiyun        };
131*4882a593Smuzhiyun    };
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun...
134*4882a593Smuzhiyun
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