1*4882a593Smuzhiyun* Solomon SSD1307 Framebuffer Driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible: Should be "solomon,<chip>fb-<bus>". The only supported bus for 5*4882a593Smuzhiyun now is i2c, and the supported chips are ssd1305, ssd1306, ssd1307 and 6*4882a593Smuzhiyun ssd1309. 7*4882a593Smuzhiyun - reg: Should contain address of the controller on the I2C bus. Most likely 8*4882a593Smuzhiyun 0x3c or 0x3d 9*4882a593Smuzhiyun - pwm: Should contain the pwm to use according to the OF device tree PWM 10*4882a593Smuzhiyun specification [0]. Only required for the ssd1307. 11*4882a593Smuzhiyun - solomon,height: Height in pixel of the screen driven by the controller 12*4882a593Smuzhiyun - solomon,width: Width in pixel of the screen driven by the controller 13*4882a593Smuzhiyun - solomon,page-offset: Offset of pages (band of 8 pixels) that the screen is 14*4882a593Smuzhiyun mapped to. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunOptional properties: 17*4882a593Smuzhiyun - reset-gpios: The GPIO used to reset the OLED display, if available. See 18*4882a593Smuzhiyun Documentation/devicetree/bindings/gpio/gpio.txt for details. 19*4882a593Smuzhiyun - vbat-supply: The supply for VBAT 20*4882a593Smuzhiyun - solomon,segment-no-remap: Display needs normal (non-inverted) data column 21*4882a593Smuzhiyun to segment mapping 22*4882a593Smuzhiyun - solomon,col-offset: Offset of columns (COL/SEG) that the screen is mapped to. 23*4882a593Smuzhiyun - solomon,com-seq: Display uses sequential COM pin configuration 24*4882a593Smuzhiyun - solomon,com-lrremap: Display uses left-right COM pin remap 25*4882a593Smuzhiyun - solomon,com-invdir: Display uses inverted COM pin scan direction 26*4882a593Smuzhiyun - solomon,com-offset: Number of the COM pin wired to the first display line 27*4882a593Smuzhiyun - solomon,prechargep1: Length of deselect period (phase 1) in clock cycles. 28*4882a593Smuzhiyun - solomon,prechargep2: Length of precharge period (phase 2) in clock cycles. 29*4882a593Smuzhiyun This needs to be the higher, the higher the capacitance 30*4882a593Smuzhiyun of the OLED's pixels is 31*4882a593Smuzhiyun - solomon,dclk-div: Clock divisor 1 to 16 32*4882a593Smuzhiyun - solomon,dclk-frq: Clock frequency 0 to 15, higher value means higher 33*4882a593Smuzhiyun frequency 34*4882a593Smuzhiyun - solomon,lookup-table: 8 bit value array of current drive pulse widths for 35*4882a593Smuzhiyun BANK0, and colors A, B, and C. Each value in range 36*4882a593Smuzhiyun of 31 to 63 for pulse widths of 32 to 64. Color D 37*4882a593Smuzhiyun is always width 64. 38*4882a593Smuzhiyun - solomon,area-color-enable: Display uses color mode 39*4882a593Smuzhiyun - solomon,low-power. Display runs in low power mode 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun[0]: Documentation/devicetree/bindings/pwm/pwm.txt 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunExamples: 44*4882a593Smuzhiyunssd1307: oled@3c { 45*4882a593Smuzhiyun compatible = "solomon,ssd1307fb-i2c"; 46*4882a593Smuzhiyun reg = <0x3c>; 47*4882a593Smuzhiyun pwms = <&pwm 4 3000>; 48*4882a593Smuzhiyun reset-gpios = <&gpio2 7>; 49*4882a593Smuzhiyun}; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyunssd1306: oled@3c { 52*4882a593Smuzhiyun compatible = "solomon,ssd1306fb-i2c"; 53*4882a593Smuzhiyun reg = <0x3c>; 54*4882a593Smuzhiyun pwms = <&pwm 4 3000>; 55*4882a593Smuzhiyun reset-gpios = <&gpio2 7>; 56*4882a593Smuzhiyun solomon,com-lrremap; 57*4882a593Smuzhiyun solomon,com-invdir; 58*4882a593Smuzhiyun solomon,com-offset = <32>; 59*4882a593Smuzhiyun solomon,lookup-table = /bits/ 8 <0x3f 0x3f 0x3f 0x3f>; 60*4882a593Smuzhiyun}; 61