xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/snps,arcpgu.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunARC PGU
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunThis is a display controller found on several development boards produced
4*4882a593Smuzhiyunby Synopsys. The ARC PGU is an RGB streamer that reads the data from a
5*4882a593Smuzhiyunframebuffer and sends it to a single digital encoder (usually HDMI).
6*4882a593Smuzhiyun
7*4882a593SmuzhiyunRequired properties:
8*4882a593Smuzhiyun  - compatible: "snps,arcpgu"
9*4882a593Smuzhiyun  - reg: Physical base address and length of the controller's registers.
10*4882a593Smuzhiyun  - clocks: A list of phandle + clock-specifier pairs, one for each
11*4882a593Smuzhiyun    entry in 'clock-names'.
12*4882a593Smuzhiyun  - clock-names: A list of clock names. For ARC PGU it should contain:
13*4882a593Smuzhiyun      - "pxlclk" for the clock feeding the output PLL of the controller.
14*4882a593Smuzhiyun
15*4882a593SmuzhiyunRequired sub-nodes:
16*4882a593Smuzhiyun  - port: The PGU connection to an encoder chip.
17*4882a593Smuzhiyun
18*4882a593SmuzhiyunExample:
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun/ {
21*4882a593Smuzhiyun	...
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	pgu@XXXXXXXX {
24*4882a593Smuzhiyun		compatible = "snps,arcpgu";
25*4882a593Smuzhiyun		reg = <0xXXXXXXXX 0x400>;
26*4882a593Smuzhiyun		clocks = <&clock_node>;
27*4882a593Smuzhiyun		clock-names = "pxlclk";
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun		port {
30*4882a593Smuzhiyun			pgu_output: endpoint {
31*4882a593Smuzhiyun				remote-endpoint = <&hdmi_enc_input>;
32*4882a593Smuzhiyun			};
33*4882a593Smuzhiyun		};
34*4882a593Smuzhiyun	};
35*4882a593Smuzhiyun};
36