1Rockchip MIPI CSI HOST 2================================ 3 4Required properties: 5- compatible: must be one of: 6 "rockchip,rk1808-mipi-csi". 7- reg: Represent the physical address range of the controller. 8- interrupts: Represent the controller's interrupt to the CPU(s). 9- clocks, clock-names: Phandles to the controller's APB clock(pclk) as 10 described in [1]. 11- resets : phandle to the reset of MIPI CSI APB Clock. 12- reset-names : should be "apb". 13- rockchip,grf: this soc should set GRF regs to mux vopl/vopb. 14- #address-cells: Should be <1>. 15- #size-cells: Should be <0>. 16- ports: contain a port node with endpoint definitions as defined in [2]. 17 For vopb,set the reg = <0> and set the reg = <1> for vopl. 18 19Optional properties 20- clocks, clock-names: 21 phandle to the SNPS-PHY config clock, name should be "phy_cfg". 22 phandle to the SNPS-PHY PLL reference clock, name should be "ref". 23 phandle to the Non-SNPS PHY high speed clock, name should be "hs_clk". 24 phandle to the h2p bridge clock, name should be "h2p". 25- phys: phandle to Non-SNPS PHY node 26- phy-names: the string "mipi_dphy" when is found in a node, along with "phys" 27 attribute, provides phandle to MIPI PHY node 28- rockchip,dual-channel: for dual-channel panel, if not, don't configure 29- rockchip,lane-rate: manually configure lane-rate, not necessary. 30 31[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 32[2] Documentation/devicetree/bindings/media/video-interfaces.txt 33[3] Documentation/devicetree/bindings/reset/reset.txt 34 35Example: 36 37For Rockchip RK1808: 38 39 csi: csi@ffb20000 { 40 compatible = "rockchip,rk1808-mipi-csi"; 41 clocks = <&cru PCLK_MIPI_CSI0>, <&mipi_dphy>; 42 clock-names = "pclk", "hs_clk"; 43 phys = <&mipi_dphy>; 44 phy-names = "mipi_dphy"; 45 resets = <&cru SRST_MIPICSI>; 46 reset-names = "apb"; 47 ... 48 49 ports { 50 port { 51 csi_in_vop: endpoint { 52 remote-endpoint = <&vop_out_csi>; 53 }; 54 }; 55 }; 56 }; 57