1*4882a593SmuzhiyunRockchip RK618 display bridge bindings 2*4882a593Smuzhiyun====================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunVIF Module 5*4882a593Smuzhiyun---------- 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible: value should be one of the following: 9*4882a593Smuzhiyun "rockchip,rk618-vif" 10*4882a593Smuzhiyun- clocks: must include clock specifiers corresponding to entries in the 11*4882a593Smuzhiyun clock-names property. 12*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 13*4882a593Smuzhiyun- clock-names: list of clock names sorted in the same order as the clocks 14*4882a593Smuzhiyun property. Must contain "vif", "vif_pre". 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunRequired nodes: 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunThe connections to the video ports are modeled using the OF graph 19*4882a593Smuzhiyunbindings specified in Documentation/devicetree/bindings/graph.txt. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunExample: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun&rk618 { 24*4882a593Smuzhiyun status = "okay"; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun vif { 27*4882a593Smuzhiyun compatible = "rockchip,rk618-vif"; 28*4882a593Smuzhiyun clocks = <&CRU VIF0_CLK>, <&CRU VIF0_PRE_CLK>; 29*4882a593Smuzhiyun clock-names = "vif", "vif_pre"; 30*4882a593Smuzhiyun status = "okay"; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun ports { 33*4882a593Smuzhiyun #address-cells = <1>; 34*4882a593Smuzhiyun #size-cells = <0>; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun port@0 { 37*4882a593Smuzhiyun reg = <0>; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun bridge_input_rgb: endpoint { 40*4882a593Smuzhiyun remote-endpoint = <&rgb_out_bridge>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun port@1 { 45*4882a593Smuzhiyun reg = <1>; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun vif_output_hdmi: endpoint { 48*4882a593Smuzhiyun remote-endpoint = <&hdmi_input_vif>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun}; 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunSCALER Module 56*4882a593Smuzhiyun---------- 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunRequired properties: 59*4882a593Smuzhiyun- compatible: value should be one of the following: 60*4882a593Smuzhiyun "rockchip,rk618-scaler" 61*4882a593Smuzhiyun- clocks: must include clock specifiers corresponding to entries in the 62*4882a593Smuzhiyun clock-names property. 63*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 64*4882a593Smuzhiyun- clock-names: list of clock names sorted in the same order as the clocks 65*4882a593Smuzhiyun property. Must contain "scaler", "vif", "dither". 66*4882a593Smuzhiyun 67*4882a593SmuzhiyunRequired nodes: 68*4882a593Smuzhiyun 69*4882a593SmuzhiyunThe connections to the video ports are modeled using the OF graph 70*4882a593Smuzhiyunbindings specified in Documentation/devicetree/bindings/graph.txt. 71*4882a593Smuzhiyun 72*4882a593SmuzhiyunExample: 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun&rk618 { 75*4882a593Smuzhiyun status = "okay"; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun scaler { 78*4882a593Smuzhiyun compatible = "rockchip,rk618-scaler"; 79*4882a593Smuzhiyun clocks = <&CRU SCALER_CLK>, <&CRU DITHER_CLK>, <&CRU VIF0_CLK>; 80*4882a593Smuzhiyun clock-names = "scaler", "dither", "vif"; 81*4882a593Smuzhiyun status = "okay"; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun ports { 84*4882a593Smuzhiyun #address-cells = <1>; 85*4882a593Smuzhiyun #size-cells = <0>; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun port@0 { 88*4882a593Smuzhiyun reg = <0>; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun scaler_input_hdmi: endpoint { 91*4882a593Smuzhiyun remote-endpoint = <&hdmi_output_scaler>; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun port@1 { 96*4882a593Smuzhiyun reg = <1>; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun scaler_output_lvds: endpoint { 99*4882a593Smuzhiyun remote-endpoint = <&lvds_input_scaler>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun}; 105*4882a593Smuzhiyun 106*4882a593SmuzhiyunLVDS Connector 107*4882a593Smuzhiyun------------ 108*4882a593Smuzhiyun 109*4882a593SmuzhiyunRequired properties: 110*4882a593Smuzhiyun- compatible: value should be one of the following: 111*4882a593Smuzhiyun "rockchip,rk618-lvds" 112*4882a593Smuzhiyun- clocks: must include clock specifiers corresponding to entries in the 113*4882a593Smuzhiyun clock-names property. 114*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 115*4882a593Smuzhiyun- clock-names: list of clock names sorted in the same order as the clocks 116*4882a593Smuzhiyun property. Must contain "lvds". 117*4882a593Smuzhiyun 118*4882a593SmuzhiyunOptional properties: 119*4882a593Smuzhiyun- dual-channel: boolean. if it exists, enable dual channel mode 120*4882a593Smuzhiyun 121*4882a593SmuzhiyunRequired nodes: 122*4882a593Smuzhiyun 123*4882a593SmuzhiyunThe connections to the video ports are modeled using the OF graph 124*4882a593Smuzhiyunbindings specified in Documentation/devicetree/bindings/graph.txt. 125*4882a593Smuzhiyun 126*4882a593SmuzhiyunExample: 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun&rk618 { 129*4882a593Smuzhiyun status = "okay"; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun lvds { 132*4882a593Smuzhiyun compatible = "rockchip,rk618-lvds"; 133*4882a593Smuzhiyun clocks = <&CRU LVDS_CLK>; 134*4882a593Smuzhiyun clock-names = "lvds"; 135*4882a593Smuzhiyun status = "okay"; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun ports { 138*4882a593Smuzhiyun #address-cells = <1>; 139*4882a593Smuzhiyun #size-cells = <0>; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun port@0 { 142*4882a593Smuzhiyun reg = <0>; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun bridge_input_rgb: endpoint { 145*4882a593Smuzhiyun remote-endpoint = <&rgb_out_bridge>; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun port@1 { 150*4882a593Smuzhiyun reg = <1>; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun lvds_output_panel: endpoint { 153*4882a593Smuzhiyun remote-endpoint = <&panel_input_lvds>; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun}; 159*4882a593Smuzhiyun 160*4882a593SmuzhiyunRGB Connector 161*4882a593Smuzhiyun------------ 162*4882a593Smuzhiyun 163*4882a593SmuzhiyunRequired properties: 164*4882a593Smuzhiyun- compatible: value should be one of the following: 165*4882a593Smuzhiyun "rockchip,rk618-rgb" 166*4882a593Smuzhiyun- clocks: must include clock specifiers corresponding to entries in the 167*4882a593Smuzhiyun clock-names property. 168*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 169*4882a593Smuzhiyun- clock-names: list of clock names sorted in the same order as the clocks 170*4882a593Smuzhiyun property. Must contain "rgb". 171*4882a593Smuzhiyun 172*4882a593SmuzhiyunRequired nodes: 173*4882a593Smuzhiyun 174*4882a593SmuzhiyunThe connections to the video ports are modeled using the OF graph 175*4882a593Smuzhiyunbindings specified in Documentation/devicetree/bindings/graph.txt. 176*4882a593Smuzhiyun 177*4882a593SmuzhiyunExample: 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun&rk618 { 180*4882a593Smuzhiyun status = "okay"; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun rgb { 183*4882a593Smuzhiyun compatible = "rockchip,rk618-rgb"; 184*4882a593Smuzhiyun clocks = <&CRU RGB_CLK>; 185*4882a593Smuzhiyun clock-names = "rgb"; 186*4882a593Smuzhiyun status = "okay"; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun ports { 189*4882a593Smuzhiyun #address-cells = <1>; 190*4882a593Smuzhiyun #size-cells = <0>; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun port@0 { 193*4882a593Smuzhiyun reg = <0>; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun bridge_input_rgb: endpoint { 196*4882a593Smuzhiyun remote-endpoint = <&rgb_out_bridge>; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun }; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun port@1 { 201*4882a593Smuzhiyun reg = <1>; 202*4882a593Smuzhiyun #address-cells = <1>; 203*4882a593Smuzhiyun #size-cells = <0>; 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun rgb_output_panel: endpoint@0 { 206*4882a593Smuzhiyun reg = <0>; 207*4882a593Smuzhiyun remote-endpoint = <&panel_input_rgb>; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun}; 213*4882a593Smuzhiyun 214*4882a593SmuzhiyunHDMI Connector 215*4882a593Smuzhiyun------------ 216*4882a593Smuzhiyun 217*4882a593SmuzhiyunRequired properties: 218*4882a593Smuzhiyun- compatible: value should be one of the following: 219*4882a593Smuzhiyun "rockchip,rk618-hdmi" 220*4882a593Smuzhiyun- clocks: must include clock specifiers corresponding to entries in the 221*4882a593Smuzhiyun clock-names property. 222*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 223*4882a593Smuzhiyun- clock-names: list of clock names sorted in the same order as the clocks 224*4882a593Smuzhiyun property. Must contain "hdmi". 225*4882a593Smuzhiyun- interrupt-parent: phandle for the interrupt gpio controller 226*4882a593Smuzhiyun- interrupts: GPIO interrupt to which the chip is connected 227*4882a593Smuzhiyun 228*4882a593SmuzhiyunRequired nodes: 229*4882a593Smuzhiyun 230*4882a593SmuzhiyunThe connections to the video ports are modeled using the OF graph 231*4882a593Smuzhiyunbindings specified in Documentation/devicetree/bindings/graph.txt. 232*4882a593Smuzhiyun 233*4882a593SmuzhiyunExample: 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun&rk618 { 236*4882a593Smuzhiyun status = "okay"; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun hdmi { 239*4882a593Smuzhiyun compatible = "rockchip,rk618-hdmi"; 240*4882a593Smuzhiyun clocks = <&CRU HDMI_CLK>; 241*4882a593Smuzhiyun clock-names = "hdmi"; 242*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 243*4882a593Smuzhiyun interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 244*4882a593Smuzhiyun status = "okay"; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun ports { 247*4882a593Smuzhiyun #address-cells = <1>; 248*4882a593Smuzhiyun #size-cells = <0>; 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun port@0 { 251*4882a593Smuzhiyun reg = <0>; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun bridge_input_rgb: endpoint { 254*4882a593Smuzhiyun remote-endpoint = <&rgb_out_bridge>; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun }; 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun}; 260*4882a593Smuzhiyun 261*4882a593SmuzhiyunDSI Connector 262*4882a593Smuzhiyun------------ 263*4882a593Smuzhiyun 264*4882a593SmuzhiyunRequired properties: 265*4882a593Smuzhiyun- compatible: value should be one of the following: 266*4882a593Smuzhiyun "rockchip,rk618-dsi" 267*4882a593Smuzhiyun- clocks: must include clock specifiers corresponding to entries in the 268*4882a593Smuzhiyun clock-names property. 269*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 270*4882a593Smuzhiyun- clock-names: list of clock names sorted in the same order as the clocks 271*4882a593Smuzhiyun property. Must contain "dsi". 272*4882a593Smuzhiyun- #address-cells, #size-cells: should be set respectively to <1> and <0>. 273*4882a593Smuzhiyun 274*4882a593SmuzhiyunOptional properties: 275*4882a593Smuzhiyun- rockchip,lane-rate: specifies the lane data rate [Mbps] 276*4882a593Smuzhiyun 277*4882a593SmuzhiyunChild nodes: 278*4882a593Smuzhiyun Should contain DSI peripheral nodes 279*4882a593Smuzhiyun (see Documentation/devicetree/bindings/display/mipi-dsi-bus.txt). 280*4882a593Smuzhiyun 281*4882a593SmuzhiyunRequired nodes: 282*4882a593Smuzhiyun 283*4882a593SmuzhiyunThe connections to the video ports are modeled using the OF graph 284*4882a593Smuzhiyunbindings specified in Documentation/devicetree/bindings/graph.txt. 285*4882a593Smuzhiyun 286*4882a593SmuzhiyunExample: 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun&rk618 { 289*4882a593Smuzhiyun status = "okay"; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun dsi { 292*4882a593Smuzhiyun compatible = "rockchip,rk618-dsi"; 293*4882a593Smuzhiyun clocks = <&CRU MIPI_CLK>; 294*4882a593Smuzhiyun clock-names = "dsi"; 295*4882a593Smuzhiyun #address-cells = <1>; 296*4882a593Smuzhiyun #size-cells = <0>; 297*4882a593Smuzhiyun status = "okay"; 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun ports { 300*4882a593Smuzhiyun #address-cells = <1>; 301*4882a593Smuzhiyun #size-cells = <0>; 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun port@0 { 304*4882a593Smuzhiyun reg = <0>; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun bridge_input_rgb: endpoint { 307*4882a593Smuzhiyun remote-endpoint = <&rgb_out_bridge>; 308*4882a593Smuzhiyun }; 309*4882a593Smuzhiyun }; 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun }; 312*4882a593Smuzhiyun}; 313