xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3066-hdmi.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Rockchip rk3066 HDMI controller
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Sandy Huang <hjc@rock-chips.com>
11*4882a593Smuzhiyun  - Heiko Stuebner <heiko@sntech.de>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyunproperties:
14*4882a593Smuzhiyun  compatible:
15*4882a593Smuzhiyun    const: rockchip,rk3066-hdmi
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun  reg:
18*4882a593Smuzhiyun    maxItems: 1
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun  interrupts:
21*4882a593Smuzhiyun    maxItems: 1
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun  clocks:
24*4882a593Smuzhiyun    maxItems: 1
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun  clock-names:
27*4882a593Smuzhiyun    const: hclk
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun  pinctrl-0:
30*4882a593Smuzhiyun    maxItems: 2
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun  pinctrl-names:
33*4882a593Smuzhiyun    const: default
34*4882a593Smuzhiyun    description:
35*4882a593Smuzhiyun      Switch the iomux for the HPD/I2C pins to HDMI function.
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun  power-domains:
38*4882a593Smuzhiyun    maxItems: 1
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun  rockchip,grf:
41*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/phandle
42*4882a593Smuzhiyun    description:
43*4882a593Smuzhiyun      This soc uses GRF regs to switch the HDMI TX input between vop0 and vop1.
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun  ports:
46*4882a593Smuzhiyun    type: object
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun    properties:
49*4882a593Smuzhiyun      "#address-cells":
50*4882a593Smuzhiyun        const: 1
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun      "#size-cells":
53*4882a593Smuzhiyun        const: 0
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun      port@0:
56*4882a593Smuzhiyun        type: object
57*4882a593Smuzhiyun        description:
58*4882a593Smuzhiyun          Port node with two endpoints, numbered 0 and 1,
59*4882a593Smuzhiyun          connected respectively to vop0 and vop1.
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun      port@1:
62*4882a593Smuzhiyun        type: object
63*4882a593Smuzhiyun        description:
64*4882a593Smuzhiyun          Port node with one endpoint connected to a hdmi-connector node.
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun    required:
67*4882a593Smuzhiyun      - "#address-cells"
68*4882a593Smuzhiyun      - "#size-cells"
69*4882a593Smuzhiyun      - port@0
70*4882a593Smuzhiyun      - port@1
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun    additionalProperties: false
73*4882a593Smuzhiyun
74*4882a593Smuzhiyunrequired:
75*4882a593Smuzhiyun  - compatible
76*4882a593Smuzhiyun  - reg
77*4882a593Smuzhiyun  - interrupts
78*4882a593Smuzhiyun  - clocks
79*4882a593Smuzhiyun  - clock-names
80*4882a593Smuzhiyun  - pinctrl-0
81*4882a593Smuzhiyun  - pinctrl-names
82*4882a593Smuzhiyun  - power-domains
83*4882a593Smuzhiyun  - rockchip,grf
84*4882a593Smuzhiyun  - ports
85*4882a593Smuzhiyun
86*4882a593SmuzhiyunadditionalProperties: false
87*4882a593Smuzhiyun
88*4882a593Smuzhiyunexamples:
89*4882a593Smuzhiyun  - |
90*4882a593Smuzhiyun    #include <dt-bindings/clock/rk3066a-cru.h>
91*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
92*4882a593Smuzhiyun    #include <dt-bindings/pinctrl/rockchip.h>
93*4882a593Smuzhiyun    #include <dt-bindings/power/rk3066-power.h>
94*4882a593Smuzhiyun    hdmi: hdmi@10116000 {
95*4882a593Smuzhiyun      compatible = "rockchip,rk3066-hdmi";
96*4882a593Smuzhiyun      reg = <0x10116000 0x2000>;
97*4882a593Smuzhiyun      interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
98*4882a593Smuzhiyun      clocks = <&cru HCLK_HDMI>;
99*4882a593Smuzhiyun      clock-names = "hclk";
100*4882a593Smuzhiyun      pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
101*4882a593Smuzhiyun      pinctrl-names = "default";
102*4882a593Smuzhiyun      power-domains = <&power RK3066_PD_VIO>;
103*4882a593Smuzhiyun      rockchip,grf = <&grf>;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun      ports {
106*4882a593Smuzhiyun        #address-cells = <1>;
107*4882a593Smuzhiyun        #size-cells = <0>;
108*4882a593Smuzhiyun        hdmi_in: port@0 {
109*4882a593Smuzhiyun          reg = <0>;
110*4882a593Smuzhiyun          #address-cells = <1>;
111*4882a593Smuzhiyun          #size-cells = <0>;
112*4882a593Smuzhiyun          hdmi_in_vop0: endpoint@0 {
113*4882a593Smuzhiyun            reg = <0>;
114*4882a593Smuzhiyun            remote-endpoint = <&vop0_out_hdmi>;
115*4882a593Smuzhiyun          };
116*4882a593Smuzhiyun          hdmi_in_vop1: endpoint@1 {
117*4882a593Smuzhiyun            reg = <1>;
118*4882a593Smuzhiyun            remote-endpoint = <&vop1_out_hdmi>;
119*4882a593Smuzhiyun          };
120*4882a593Smuzhiyun        };
121*4882a593Smuzhiyun        hdmi_out: port@1 {
122*4882a593Smuzhiyun          reg = <1>;
123*4882a593Smuzhiyun          hdmi_out_con: endpoint {
124*4882a593Smuzhiyun            remote-endpoint = <&hdmi_con_in>;
125*4882a593Smuzhiyun          };
126*4882a593Smuzhiyun        };
127*4882a593Smuzhiyun      };
128*4882a593Smuzhiyun    };
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun    pinctrl {
131*4882a593Smuzhiyun      hdmi {
132*4882a593Smuzhiyun        hdmi_hpd: hdmi-hpd {
133*4882a593Smuzhiyun          rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
134*4882a593Smuzhiyun        };
135*4882a593Smuzhiyun        hdmii2c_xfer: hdmii2c-xfer {
136*4882a593Smuzhiyun          rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
137*4882a593Smuzhiyun                          <0 RK_PA2 1 &pcfg_pull_none>;
138*4882a593Smuzhiyun        };
139*4882a593Smuzhiyun      };
140*4882a593Smuzhiyun    };
141