1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/panel/sharp,lq101r1sx01.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Sharp Microelectronics 10.1" WQXGA TFT LCD panel 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Thierry Reding <treding@nvidia.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun This panel requires a dual-channel DSI host to operate. It supports two modes: 14*4882a593Smuzhiyun - left-right: each channel drives the left or right half of the screen 15*4882a593Smuzhiyun - even-odd: each channel drives the even or odd lines of the screen 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun Each of the DSI channels controls a separate DSI peripheral. The peripheral 18*4882a593Smuzhiyun driven by the first link (DSI-LINK1), left or even, is considered the primary 19*4882a593Smuzhiyun peripheral and controls the device. The 'link2' property contains a phandle 20*4882a593Smuzhiyun to the peripheral driven by the second link (DSI-LINK2, right or odd). 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun Note that in video mode the DSI-LINK1 interface always provides the left/even 23*4882a593Smuzhiyun pixels and DSI-LINK2 always provides the right/odd pixels. In command mode it 24*4882a593Smuzhiyun is possible to program either link to drive the left/even or right/odd pixels 25*4882a593Smuzhiyun but for the sake of consistency this binding assumes that the same assignment 26*4882a593Smuzhiyun is chosen as for video mode. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunallOf: 29*4882a593Smuzhiyun - $ref: panel-common.yaml# 30*4882a593Smuzhiyun 31*4882a593Smuzhiyunproperties: 32*4882a593Smuzhiyun compatible: 33*4882a593Smuzhiyun const: sharp,lq101r1sx01 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun reg: true 36*4882a593Smuzhiyun power-supply: true 37*4882a593Smuzhiyun backlight: true 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun link2: 40*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/phandle 41*4882a593Smuzhiyun description: | 42*4882a593Smuzhiyun phandle to the DSI peripheral on the secondary link. Note that the 43*4882a593Smuzhiyun presence of this property marks the containing node as DSI-LINK1 44*4882a593Smuzhiyun 45*4882a593Smuzhiyunrequired: 46*4882a593Smuzhiyun - compatible 47*4882a593Smuzhiyun - reg 48*4882a593Smuzhiyun 49*4882a593Smuzhiyunif: 50*4882a593Smuzhiyun required: 51*4882a593Smuzhiyun - link2 52*4882a593Smuzhiyunthen: 53*4882a593Smuzhiyun required: 54*4882a593Smuzhiyun - power-supply 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunadditionalProperties: false 57*4882a593Smuzhiyun 58*4882a593Smuzhiyunexamples: 59*4882a593Smuzhiyun - | 60*4882a593Smuzhiyun dsi0: dsi@fd922800 { 61*4882a593Smuzhiyun #address-cells = <1>; 62*4882a593Smuzhiyun #size-cells = <0>; 63*4882a593Smuzhiyun reg = <0xfd922800 0x200>; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun panel: panel@0 { 66*4882a593Smuzhiyun compatible = "sharp,lq101r1sx01"; 67*4882a593Smuzhiyun reg = <0>; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun link2 = <&secondary>; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun power-supply = <&power>; 72*4882a593Smuzhiyun backlight = <&backlight>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun dsi1: dsi@fd922a00 { 77*4882a593Smuzhiyun #address-cells = <1>; 78*4882a593Smuzhiyun #size-cells = <0>; 79*4882a593Smuzhiyun reg = <0xfd922a00 0x200>; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun secondary: panel@0 { 82*4882a593Smuzhiyun compatible = "sharp,lq101r1sx01"; 83*4882a593Smuzhiyun reg = <0>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun... 88