1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/panel/lvds.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: LVDS Display Panel 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 11*4882a593Smuzhiyun - Thierry Reding <thierry.reding@gmail.com> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: |+ 14*4882a593Smuzhiyun LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple 15*4882a593Smuzhiyun incompatible data link layers have been used over time to transmit image data 16*4882a593Smuzhiyun to LVDS panels. This bindings supports display panels compatible with the 17*4882a593Smuzhiyun following specifications. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February 20*4882a593Smuzhiyun 1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA) 21*4882a593Smuzhiyun [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National 22*4882a593Smuzhiyun Semiconductor 23*4882a593Smuzhiyun [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video 24*4882a593Smuzhiyun Electronics Standards Association (VESA) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun Device compatible with those specifications have been marketed under the 27*4882a593Smuzhiyun FPD-Link and FlatLink brands. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunallOf: 30*4882a593Smuzhiyun - $ref: panel-common.yaml# 31*4882a593Smuzhiyun 32*4882a593Smuzhiyunproperties: 33*4882a593Smuzhiyun compatible: 34*4882a593Smuzhiyun contains: 35*4882a593Smuzhiyun const: panel-lvds 36*4882a593Smuzhiyun description: 37*4882a593Smuzhiyun Shall contain "panel-lvds" in addition to a mandatory panel-specific 38*4882a593Smuzhiyun compatible string defined in individual panel bindings. The "panel-lvds" 39*4882a593Smuzhiyun value shall never be used on its own. 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun data-mapping: 42*4882a593Smuzhiyun enum: 43*4882a593Smuzhiyun - jeida-18 44*4882a593Smuzhiyun - jeida-24 45*4882a593Smuzhiyun - vesa-24 46*4882a593Smuzhiyun description: | 47*4882a593Smuzhiyun The color signals mapping order. 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun LVDS data mappings are defined as follows. 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and 52*4882a593Smuzhiyun [VESA] specifications. Data are transferred as follows on 3 LVDS lanes. 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun Slot 0 1 2 3 4 5 6 55*4882a593Smuzhiyun ________________ _________________ 56*4882a593Smuzhiyun Clock \_______________________/ 57*4882a593Smuzhiyun ______ ______ ______ ______ ______ ______ ______ 58*4882a593Smuzhiyun DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< 59*4882a593Smuzhiyun DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< 60*4882a593Smuzhiyun DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI] 63*4882a593Smuzhiyun specifications. Data are transferred as follows on 4 LVDS lanes. 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun Slot 0 1 2 3 4 5 6 66*4882a593Smuzhiyun ________________ _________________ 67*4882a593Smuzhiyun Clock \_______________________/ 68*4882a593Smuzhiyun ______ ______ ______ ______ ______ ______ ______ 69*4882a593Smuzhiyun DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__>< 70*4882a593Smuzhiyun DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__>< 71*4882a593Smuzhiyun DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__>< 72*4882a593Smuzhiyun DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__>< 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification. 75*4882a593Smuzhiyun Data are transferred as follows on 4 LVDS lanes. 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun Slot 0 1 2 3 4 5 6 78*4882a593Smuzhiyun ________________ _________________ 79*4882a593Smuzhiyun Clock \_______________________/ 80*4882a593Smuzhiyun ______ ______ ______ ______ ______ ______ ______ 81*4882a593Smuzhiyun DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< 82*4882a593Smuzhiyun DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< 83*4882a593Smuzhiyun DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< 84*4882a593Smuzhiyun DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__>< 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun Control signals are mapped as follows. 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun CTL0: HSync 89*4882a593Smuzhiyun CTL1: VSync 90*4882a593Smuzhiyun CTL2: Data Enable 91*4882a593Smuzhiyun CTL3: 0 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun data-mirror: 94*4882a593Smuzhiyun type: boolean 95*4882a593Smuzhiyun description: 96*4882a593Smuzhiyun If set, reverse the bit order described in the data mappings below on all 97*4882a593Smuzhiyun data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6. 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun port: true 100*4882a593Smuzhiyun ports: true 101*4882a593Smuzhiyun 102*4882a593Smuzhiyunrequired: 103*4882a593Smuzhiyun - compatible 104*4882a593Smuzhiyun - data-mapping 105*4882a593Smuzhiyun - width-mm 106*4882a593Smuzhiyun - height-mm 107*4882a593Smuzhiyun - panel-timing 108*4882a593Smuzhiyun 109*4882a593SmuzhiyunoneOf: 110*4882a593Smuzhiyun - required: 111*4882a593Smuzhiyun - port 112*4882a593Smuzhiyun - required: 113*4882a593Smuzhiyun - ports 114*4882a593Smuzhiyun 115*4882a593SmuzhiyunadditionalProperties: true 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun... 118