1*4882a593Smuzhiyun* Freescale MXS LCD Interface (LCDIF) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunNew bindings: 4*4882a593Smuzhiyun============= 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun- compatible: Should be "fsl,imx23-lcdif" for i.MX23. 7*4882a593Smuzhiyun Should be "fsl,imx28-lcdif" for i.MX28. 8*4882a593Smuzhiyun Should be "fsl,imx6sx-lcdif" for i.MX6SX. 9*4882a593Smuzhiyun Should be "fsl,imx8mq-lcdif" for i.MX8MQ. 10*4882a593Smuzhiyun- reg: Address and length of the register set for LCDIF 11*4882a593Smuzhiyun- interrupts: Should contain LCDIF interrupt 12*4882a593Smuzhiyun- clocks: A list of phandle + clock-specifier pairs, one for each 13*4882a593Smuzhiyun entry in 'clock-names'. 14*4882a593Smuzhiyun- clock-names: A list of clock names. For MXSFB it should contain: 15*4882a593Smuzhiyun - "pix" for the LCDIF block clock 16*4882a593Smuzhiyun - (MX6SX-only) "axi", "disp_axi" for the bus interface clock 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunRequired sub-nodes: 19*4882a593Smuzhiyun - port: The connection to an encoder chip. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunExample: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun lcdif1: display-controller@2220000 { 24*4882a593Smuzhiyun compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; 25*4882a593Smuzhiyun reg = <0x02220000 0x4000>; 26*4882a593Smuzhiyun interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 27*4882a593Smuzhiyun clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, 28*4882a593Smuzhiyun <&clks IMX6SX_CLK_LCDIF_APB>, 29*4882a593Smuzhiyun <&clks IMX6SX_CLK_DISPLAY_AXI>; 30*4882a593Smuzhiyun clock-names = "pix", "axi", "disp_axi"; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun port { 33*4882a593Smuzhiyun parallel_out: endpoint { 34*4882a593Smuzhiyun remote-endpoint = <&panel_in_parallel>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunDeprecated bindings: 40*4882a593Smuzhiyun==================== 41*4882a593SmuzhiyunRequired properties: 42*4882a593Smuzhiyun- compatible: Should be "fsl,imx23-lcdif" for i.MX23. 43*4882a593Smuzhiyun Should be "fsl,imx28-lcdif" for i.MX28. 44*4882a593Smuzhiyun- reg: Address and length of the register set for LCDIF 45*4882a593Smuzhiyun- interrupts: Should contain LCDIF interrupts 46*4882a593Smuzhiyun- display: phandle to display node (see below for details) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun* display node 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunRequired properties: 51*4882a593Smuzhiyun- bits-per-pixel: <16> for RGB565, <32> for RGB888/666. 52*4882a593Smuzhiyun- bus-width: number of data lines. Could be <8>, <16>, <18> or <24>. 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunRequired sub-node: 55*4882a593Smuzhiyun- display-timings: Refer to binding doc display-timing.txt for details. 56*4882a593Smuzhiyun 57*4882a593SmuzhiyunExamples: 58*4882a593Smuzhiyun 59*4882a593Smuzhiyunlcdif@80030000 { 60*4882a593Smuzhiyun compatible = "fsl,imx28-lcdif"; 61*4882a593Smuzhiyun reg = <0x80030000 2000>; 62*4882a593Smuzhiyun interrupts = <38 86>; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun display: display { 65*4882a593Smuzhiyun bits-per-pixel = <32>; 66*4882a593Smuzhiyun bus-width = <24>; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun display-timings { 69*4882a593Smuzhiyun native-mode = <&timing0>; 70*4882a593Smuzhiyun timing0: timing0 { 71*4882a593Smuzhiyun clock-frequency = <33500000>; 72*4882a593Smuzhiyun hactive = <800>; 73*4882a593Smuzhiyun vactive = <480>; 74*4882a593Smuzhiyun hfront-porch = <164>; 75*4882a593Smuzhiyun hback-porch = <89>; 76*4882a593Smuzhiyun hsync-len = <10>; 77*4882a593Smuzhiyun vback-porch = <23>; 78*4882a593Smuzhiyun vfront-porch = <10>; 79*4882a593Smuzhiyun vsync-len = <10>; 80*4882a593Smuzhiyun hsync-active = <0>; 81*4882a593Smuzhiyun vsync-active = <0>; 82*4882a593Smuzhiyun de-active = <1>; 83*4882a593Smuzhiyun pixelclk-active = <0>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun}; 88