xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/msm/mdp4.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)

Qualcomm adreno/snapdragon MDP4 display controller

Description:

This is the bindings documentation for the MDP4 display controller found in
SoCs like MSM8960, APQ8064 and MSM8660.

Required properties:
- compatible:
  * "qcom,mdp4" - mdp4
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt signal from the display controller.
- clocks: device clocks
  See ../clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required.
  * "core_clk"
  * "iface_clk"
  * "bus_clk"
  * "lut_clk"
  * "hdmi_clk"
  * "tv_clk"
- ports: contains the list of output ports from MDP. These connect to interfaces
  that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
  special case since it is a part of the MDP block itself).

  Each output port contains an endpoint that describes how it is connected to an
  external interface. These are described by the standard properties documented
  here:
	Documentation/devicetree/bindings/graph.txt
	Documentation/devicetree/bindings/media/video-interfaces.txt

  The output port mappings are:
	Port 0 -> LCDC/LVDS
	Port 1 -> DSI1 Cmd/Video
	Port 2 -> DSI2 Cmd/Video
	Port 3 -> DTV

Optional properties:
- clock-names: the following clocks are optional:
  * "lut_clk"
- qcom,lcdc-align-lsb: Boolean value indicating that LSB alignment should be
  used for LCDC. This is only valid for 18bpp panels.

Example:

/ {
	...

	hdmi: hdmi@4a00000 {
		...
		ports {
			...
			port@0 {
				reg = <0>;
				hdmi_in: endpoint {
					remote-endpoint = <&mdp_dtv_out>;
				};
			};
			...
		};
		...
	};

	...

	mdp: mdp@5100000 {
		compatible = "qcom,mdp4";
		reg = <0x05100000 0xf0000>;
		interrupts = <GIC_SPI 75 0>;
		clock-names =
		    "core_clk",
		    "iface_clk",
		    "lut_clk",
		    "hdmi_clk",
		    "tv_clk";
		clocks =
		    <&mmcc MDP_CLK>,
		    <&mmcc MDP_AHB_CLK>,
		    <&mmcc MDP_AXI_CLK>,
		    <&mmcc MDP_LUT_CLK>,
		    <&mmcc HDMI_TV_CLK>,
		    <&mmcc MDP_TV_CLK>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

				port@0 {
					reg = <0>;
					mdp_lvds_out: endpoint {
					};
				};

				port@1 {
					reg = <1>;
					mdp_dsi1_out: endpoint {
					};
				};

				port@2 {
					reg = <2>;
					mdp_dsi2_out: endpoint {
					};
				};

				port@3 {
					reg = <3>;
					mdp_dtv_out: endpoint {
						remote-endpoint = <&hdmi_in>;
					};
				};
		};
	};
};