1*4882a593SmuzhiyunMediatek DSI Device 2*4882a593Smuzhiyun=================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe Mediatek DSI function block is a sink of the display subsystem and can 5*4882a593Smuzhiyundrive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- 6*4882a593Smuzhiyunchannel output. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun- compatible: "mediatek,<chip>-dsi" 10*4882a593Smuzhiyun- the supported chips are mt2701, mt7623, mt8173 and mt8183. 11*4882a593Smuzhiyun- reg: Physical base address and length of the controller's registers 12*4882a593Smuzhiyun- interrupts: The interrupt signal from the function block. 13*4882a593Smuzhiyun- clocks: device clocks 14*4882a593Smuzhiyun See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 15*4882a593Smuzhiyun- clock-names: must contain "engine", "digital", and "hs" 16*4882a593Smuzhiyun- phys: phandle link to the MIPI D-PHY controller. 17*4882a593Smuzhiyun- phy-names: must contain "dphy" 18*4882a593Smuzhiyun- port: Output port node with endpoint definitions as described in 19*4882a593Smuzhiyun Documentation/devicetree/bindings/graph.txt. This port should be connected 20*4882a593Smuzhiyun to the input port of an attached DSI panel or DSI-to-eDP encoder chip. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunMIPI TX Configuration Module 23*4882a593Smuzhiyun============================ 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunThe MIPI TX configuration module controls the MIPI D-PHY. 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunRequired properties: 28*4882a593Smuzhiyun- compatible: "mediatek,<chip>-mipi-tx" 29*4882a593Smuzhiyun- the supported chips are mt2701, 7623, mt8173 and mt8183. 30*4882a593Smuzhiyun- reg: Physical base address and length of the controller's registers 31*4882a593Smuzhiyun- clocks: PLL reference clock 32*4882a593Smuzhiyun- clock-output-names: name of the output clock line to the DSI encoder 33*4882a593Smuzhiyun- #clock-cells: must be <0>; 34*4882a593Smuzhiyun- #phy-cells: must be <0>. 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunOptional properties: 37*4882a593Smuzhiyun- drive-strength-microamp: adjust driving current, should be 3000 ~ 6000. And 38*4882a593Smuzhiyun the step is 200. 39*4882a593Smuzhiyun- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If 40*4882a593Smuzhiyun unspecified default values shall be used. 41*4882a593Smuzhiyun- nvmem-cell-names: Should be "calibration-data" 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunExample: 44*4882a593Smuzhiyun 45*4882a593Smuzhiyunmipi_tx0: mipi-dphy@10215000 { 46*4882a593Smuzhiyun compatible = "mediatek,mt8173-mipi-tx"; 47*4882a593Smuzhiyun reg = <0 0x10215000 0 0x1000>; 48*4882a593Smuzhiyun clocks = <&clk26m>; 49*4882a593Smuzhiyun clock-output-names = "mipi_tx0_pll"; 50*4882a593Smuzhiyun #clock-cells = <0>; 51*4882a593Smuzhiyun #phy-cells = <0>; 52*4882a593Smuzhiyun drive-strength-microamp = <4600>; 53*4882a593Smuzhiyun nvmem-cells= <&mipi_tx_calibration>; 54*4882a593Smuzhiyun nvmem-cell-names = "calibration-data"; 55*4882a593Smuzhiyun}; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyundsi0: dsi@1401b000 { 58*4882a593Smuzhiyun compatible = "mediatek,mt8173-dsi"; 59*4882a593Smuzhiyun reg = <0 0x1401b000 0 0x1000>; 60*4882a593Smuzhiyun interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 61*4882a593Smuzhiyun clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, 62*4882a593Smuzhiyun <&mipi_tx0>; 63*4882a593Smuzhiyun clock-names = "engine", "digital", "hs"; 64*4882a593Smuzhiyun phys = <&mipi_tx0>; 65*4882a593Smuzhiyun phy-names = "dphy"; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun port { 68*4882a593Smuzhiyun dsi0_out: endpoint { 69*4882a593Smuzhiyun remote-endpoint = <&panel_in>; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun}; 73