1*4882a593SmuzhiyunMediatek DPI Device 2*4882a593Smuzhiyun=================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe Mediatek DPI function block is a sink of the display subsystem and 5*4882a593Smuzhiyunprovides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel 6*4882a593Smuzhiyunoutput bus. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun- compatible: "mediatek,<chip>-dpi" 10*4882a593Smuzhiyun the supported chips are mt2701, mt7623, mt8173 and mt8183. 11*4882a593Smuzhiyun- reg: Physical base address and length of the controller's registers 12*4882a593Smuzhiyun- interrupts: The interrupt signal from the function block. 13*4882a593Smuzhiyun- clocks: device clocks 14*4882a593Smuzhiyun See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 15*4882a593Smuzhiyun- clock-names: must contain "pixel", "engine", and "pll" 16*4882a593Smuzhiyun- port: Output port node with endpoint definitions as described in 17*4882a593Smuzhiyun Documentation/devicetree/bindings/graph.txt. This port should be connected 18*4882a593Smuzhiyun to the input port of an attached HDMI or LVDS encoder chip. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunOptional properties: 21*4882a593Smuzhiyun- pinctrl-names: Contain "default" and "sleep". 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyundpi0: dpi@1401d000 { 26*4882a593Smuzhiyun compatible = "mediatek,mt8173-dpi"; 27*4882a593Smuzhiyun reg = <0 0x1401d000 0 0x1000>; 28*4882a593Smuzhiyun interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 29*4882a593Smuzhiyun clocks = <&mmsys CLK_MM_DPI_PIXEL>, 30*4882a593Smuzhiyun <&mmsys CLK_MM_DPI_ENGINE>, 31*4882a593Smuzhiyun <&apmixedsys CLK_APMIXED_TVDPLL>; 32*4882a593Smuzhiyun clock-names = "pixel", "engine", "pll"; 33*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 34*4882a593Smuzhiyun pinctrl-0 = <&dpi_pin_func>; 35*4882a593Smuzhiyun pinctrl-1 = <&dpi_pin_idle>; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun port { 38*4882a593Smuzhiyun dpi0_out: endpoint { 39*4882a593Smuzhiyun remote-endpoint = <&hdmi0_in>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun}; 43