1*4882a593SmuzhiyunFreescale i.MX DRM master device 2*4882a593Smuzhiyun================================ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe freescale i.MX DRM master device is a virtual device needed to list all 5*4882a593SmuzhiyunIPU or other display interface nodes that comprise the graphics subsystem. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible: Should be "fsl,imx-display-subsystem" 9*4882a593Smuzhiyun- ports: Should contain a list of phandles pointing to display interface ports 10*4882a593Smuzhiyun of IPU devices 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunexample: 13*4882a593Smuzhiyun 14*4882a593Smuzhiyundisplay-subsystem { 15*4882a593Smuzhiyun compatible = "fsl,display-subsystem"; 16*4882a593Smuzhiyun ports = <&ipu_di0>; 17*4882a593Smuzhiyun}; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunFreescale i.MX IPUv3 21*4882a593Smuzhiyun==================== 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunRequired properties: 24*4882a593Smuzhiyun- compatible: Should be "fsl,<chip>-ipu" where <chip> is one of 25*4882a593Smuzhiyun - imx51 26*4882a593Smuzhiyun - imx53 27*4882a593Smuzhiyun - imx6q 28*4882a593Smuzhiyun - imx6qp 29*4882a593Smuzhiyun- reg: should be register base and length as documented in the 30*4882a593Smuzhiyun datasheet 31*4882a593Smuzhiyun- interrupts: Should contain sync interrupt and error interrupt, 32*4882a593Smuzhiyun in this order. 33*4882a593Smuzhiyun- resets: phandle pointing to the system reset controller and 34*4882a593Smuzhiyun reset line index, see reset/fsl,imx-src.txt for details 35*4882a593SmuzhiyunAdditional required properties for fsl,imx6qp-ipu: 36*4882a593Smuzhiyun- fsl,prg: phandle to prg node associated with this IPU instance 37*4882a593SmuzhiyunOptional properties: 38*4882a593Smuzhiyun- port@[0-3]: Port nodes with endpoint definitions as defined in 39*4882a593Smuzhiyun Documentation/devicetree/bindings/media/video-interfaces.txt. 40*4882a593Smuzhiyun Ports 0 and 1 should correspond to CSI0 and CSI1, 41*4882a593Smuzhiyun ports 2 and 3 should correspond to DI0 and DI1, respectively. 42*4882a593Smuzhiyun 43*4882a593Smuzhiyunexample: 44*4882a593Smuzhiyun 45*4882a593Smuzhiyunipu: ipu@18000000 { 46*4882a593Smuzhiyun #address-cells = <1>; 47*4882a593Smuzhiyun #size-cells = <0>; 48*4882a593Smuzhiyun compatible = "fsl,imx53-ipu"; 49*4882a593Smuzhiyun reg = <0x18000000 0x080000000>; 50*4882a593Smuzhiyun interrupts = <11 10>; 51*4882a593Smuzhiyun resets = <&src 2>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun ipu_di0: port@2 { 54*4882a593Smuzhiyun reg = <2>; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun ipu_di0_disp0: endpoint { 57*4882a593Smuzhiyun remote-endpoint = <&display_in>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun}; 61*4882a593Smuzhiyun 62*4882a593SmuzhiyunFreescale i.MX PRE (Prefetch Resolve Engine) 63*4882a593Smuzhiyun============================================ 64*4882a593Smuzhiyun 65*4882a593SmuzhiyunRequired properties: 66*4882a593Smuzhiyun- compatible: should be "fsl,imx6qp-pre" 67*4882a593Smuzhiyun- reg: should be register base and length as documented in the 68*4882a593Smuzhiyun datasheet 69*4882a593Smuzhiyun- clocks : phandle to the PRE axi clock input, as described 70*4882a593Smuzhiyun in Documentation/devicetree/bindings/clock/clock-bindings.txt and 71*4882a593Smuzhiyun Documentation/devicetree/bindings/clock/imx6q-clock.yaml. 72*4882a593Smuzhiyun- clock-names: should be "axi" 73*4882a593Smuzhiyun- interrupts: should contain the PRE interrupt 74*4882a593Smuzhiyun- fsl,iram: phandle pointing to the mmio-sram device node, that should be 75*4882a593Smuzhiyun used for the PRE SRAM double buffer. 76*4882a593Smuzhiyun 77*4882a593Smuzhiyunexample: 78*4882a593Smuzhiyun 79*4882a593Smuzhiyunpre@21c8000 { 80*4882a593Smuzhiyun compatible = "fsl,imx6qp-pre"; 81*4882a593Smuzhiyun reg = <0x021c8000 0x1000>; 82*4882a593Smuzhiyun interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 83*4882a593Smuzhiyun clocks = <&clks IMX6QDL_CLK_PRE0>; 84*4882a593Smuzhiyun clock-names = "axi"; 85*4882a593Smuzhiyun fsl,iram = <&ocram2>; 86*4882a593Smuzhiyun}; 87*4882a593Smuzhiyun 88*4882a593SmuzhiyunFreescale i.MX PRG (Prefetch Resolve Gasket) 89*4882a593Smuzhiyun============================================ 90*4882a593Smuzhiyun 91*4882a593SmuzhiyunRequired properties: 92*4882a593Smuzhiyun- compatible: should be "fsl,imx6qp-prg" 93*4882a593Smuzhiyun- reg: should be register base and length as documented in the 94*4882a593Smuzhiyun datasheet 95*4882a593Smuzhiyun- clocks : phandles to the PRG ipg and axi clock inputs, as described 96*4882a593Smuzhiyun in Documentation/devicetree/bindings/clock/clock-bindings.txt and 97*4882a593Smuzhiyun Documentation/devicetree/bindings/clock/imx6q-clock.yaml. 98*4882a593Smuzhiyun- clock-names: should be "ipg" and "axi" 99*4882a593Smuzhiyun- fsl,pres: phandles to the PRE units attached to this PRG, with the fixed 100*4882a593Smuzhiyun PRE as the first entry and the muxable PREs following. 101*4882a593Smuzhiyun 102*4882a593Smuzhiyunexample: 103*4882a593Smuzhiyun 104*4882a593Smuzhiyunprg@21cc000 { 105*4882a593Smuzhiyun compatible = "fsl,imx6qp-prg"; 106*4882a593Smuzhiyun reg = <0x021cc000 0x1000>; 107*4882a593Smuzhiyun clocks = <&clks IMX6QDL_CLK_PRG0_APB>, 108*4882a593Smuzhiyun <&clks IMX6QDL_CLK_PRG0_AXI>; 109*4882a593Smuzhiyun clock-names = "ipg", "axi"; 110*4882a593Smuzhiyun fsl,pres = <&pre1>, <&pre2>, <&pre3>; 111*4882a593Smuzhiyun}; 112*4882a593Smuzhiyun 113*4882a593SmuzhiyunParallel display support 114*4882a593Smuzhiyun======================== 115*4882a593Smuzhiyun 116*4882a593SmuzhiyunRequired properties: 117*4882a593Smuzhiyun- compatible: Should be "fsl,imx-parallel-display" 118*4882a593SmuzhiyunOptional properties: 119*4882a593Smuzhiyun- interface-pix-fmt: How this display is connected to the 120*4882a593Smuzhiyun display interface. Currently supported types: "rgb24", "rgb565", "bgr666" 121*4882a593Smuzhiyun and "lvds666". 122*4882a593Smuzhiyun- edid: verbatim EDID data block describing attached display. 123*4882a593Smuzhiyun- ddc: phandle describing the i2c bus handling the display data 124*4882a593Smuzhiyun channel 125*4882a593Smuzhiyun- port@[0-1]: Port nodes with endpoint definitions as defined in 126*4882a593Smuzhiyun Documentation/devicetree/bindings/media/video-interfaces.txt. 127*4882a593Smuzhiyun Port 0 is the input port connected to the IPU display interface, 128*4882a593Smuzhiyun port 1 is the output port connected to a panel. 129*4882a593Smuzhiyun 130*4882a593Smuzhiyunexample: 131*4882a593Smuzhiyun 132*4882a593Smuzhiyundisp0 { 133*4882a593Smuzhiyun compatible = "fsl,imx-parallel-display"; 134*4882a593Smuzhiyun edid = [edid-data]; 135*4882a593Smuzhiyun interface-pix-fmt = "rgb24"; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun port@0 { 138*4882a593Smuzhiyun reg = <0>; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun display_in: endpoint { 141*4882a593Smuzhiyun remote-endpoint = <&ipu_di0_disp0>; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun port@1 { 146*4882a593Smuzhiyun reg = <1>; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun display_out: endpoint { 149*4882a593Smuzhiyun remote-endpoint = <&panel_in>; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun}; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyunpanel { 155*4882a593Smuzhiyun ... 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun port { 158*4882a593Smuzhiyun panel_in: endpoint { 159*4882a593Smuzhiyun remote-endpoint = <&display_out>; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun}; 163