1*4882a593SmuzhiyunFreescale imx21 Framebuffer 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis framebuffer driver supports devices imx1, imx21, imx25, and imx27. 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun- compatible : "fsl,<chip>-fb", chip should be imx1 or imx21 7*4882a593Smuzhiyun- reg : Should contain 1 register ranges(address and length) 8*4882a593Smuzhiyun- interrupts : One interrupt of the fb dev 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired nodes: 11*4882a593Smuzhiyun- display: Phandle to a display node as described in 12*4882a593Smuzhiyun Documentation/devicetree/bindings/display/panel/display-timing.txt 13*4882a593Smuzhiyun Additional, the display node has to define properties: 14*4882a593Smuzhiyun - bits-per-pixel: Bits per pixel 15*4882a593Smuzhiyun - fsl,pcr: LCDC PCR value 16*4882a593Smuzhiyun A display node may optionally define 17*4882a593Smuzhiyun - fsl,aus-mode: boolean to enable AUS mode (only for imx21) 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunOptional properties: 20*4882a593Smuzhiyun- lcd-supply: Regulator for LCD supply voltage. 21*4882a593Smuzhiyun- fsl,dmacr: DMA Control Register value. This is optional. By default, the 22*4882a593Smuzhiyun register is not modified as recommended by the datasheet. 23*4882a593Smuzhiyun- fsl,lpccr: Contrast Control Register value. This property provides the 24*4882a593Smuzhiyun default value for the contrast control register. 25*4882a593Smuzhiyun If that property is omitted, the register is zeroed. 26*4882a593Smuzhiyun- fsl,lscr1: LCDC Sharp Configuration Register value. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunExample: 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun imxfb: fb@10021000 { 31*4882a593Smuzhiyun compatible = "fsl,imx21-fb"; 32*4882a593Smuzhiyun interrupts = <61>; 33*4882a593Smuzhiyun reg = <0x10021000 0x1000>; 34*4882a593Smuzhiyun display = <&display0>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun ... 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun display0: display0 { 40*4882a593Smuzhiyun model = "Primeview-PD050VL1"; 41*4882a593Smuzhiyun bits-per-pixel = <16>; 42*4882a593Smuzhiyun fsl,pcr = <0xf0c88080>; /* non-standard but required */ 43*4882a593Smuzhiyun display-timings { 44*4882a593Smuzhiyun native-mode = <&timing_disp0>; 45*4882a593Smuzhiyun timing_disp0: 640x480 { 46*4882a593Smuzhiyun hactive = <640>; 47*4882a593Smuzhiyun vactive = <480>; 48*4882a593Smuzhiyun hback-porch = <112>; 49*4882a593Smuzhiyun hfront-porch = <36>; 50*4882a593Smuzhiyun hsync-len = <32>; 51*4882a593Smuzhiyun vback-porch = <33>; 52*4882a593Smuzhiyun vfront-porch = <33>; 53*4882a593Smuzhiyun vsync-len = <2>; 54*4882a593Smuzhiyun clock-frequency = <25000000>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun }; 58