1*4882a593SmuzhiyunDevice-Tree bindings for DesignWare DSI Host Controller v1.20a driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunA DSI Host Controller resides in the middle of display controller and external 4*4882a593SmuzhiyunHDMI converter or panel. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: value should be "hisilicon,hi6220-dsi". 8*4882a593Smuzhiyun- reg: physical base address and length of dsi controller's registers. 9*4882a593Smuzhiyun- clocks: contains APB clock phandle + clock-specifier pair. 10*4882a593Smuzhiyun- clock-names: should be "pclk". 11*4882a593Smuzhiyun- ports: contains DSI controller input and output sub port. 12*4882a593Smuzhiyun The input port connects to ADE output port with the reg value "0". 13*4882a593Smuzhiyun The output port with the reg value "1", it could connect to panel or 14*4882a593Smuzhiyun any other bridge endpoints. 15*4882a593Smuzhiyun See Documentation/devicetree/bindings/graph.txt for more device graph info. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunA example of HiKey board hi6220 SoC and board specific DT entry: 18*4882a593SmuzhiyunExample: 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunSoC specific: 21*4882a593Smuzhiyun dsi: dsi@f4107800 { 22*4882a593Smuzhiyun compatible = "hisilicon,hi6220-dsi"; 23*4882a593Smuzhiyun reg = <0x0 0xf4107800 0x0 0x100>; 24*4882a593Smuzhiyun clocks = <&media_ctrl HI6220_DSI_PCLK>; 25*4882a593Smuzhiyun clock-names = "pclk"; 26*4882a593Smuzhiyun status = "disabled"; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun ports { 29*4882a593Smuzhiyun #address-cells = <1>; 30*4882a593Smuzhiyun #size-cells = <0>; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* 0 for input port */ 33*4882a593Smuzhiyun port@0 { 34*4882a593Smuzhiyun reg = <0>; 35*4882a593Smuzhiyun dsi_in: endpoint { 36*4882a593Smuzhiyun remote-endpoint = <&ade_out>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunBoard specific: 44*4882a593Smuzhiyun &dsi { 45*4882a593Smuzhiyun status = "ok"; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun ports { 48*4882a593Smuzhiyun /* 1 for output port */ 49*4882a593Smuzhiyun port@1 { 50*4882a593Smuzhiyun reg = <1>; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun dsi_out0: endpoint@0 { 53*4882a593Smuzhiyun remote-endpoint = <&adv7533_in>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun &i2c2 { 60*4882a593Smuzhiyun ... 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun adv7533: adv7533@39 { 63*4882a593Smuzhiyun ... 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun port { 66*4882a593Smuzhiyun adv7533_in: endpoint { 67*4882a593Smuzhiyun remote-endpoint = <&dsi_out0>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73