1*4882a593SmuzhiyunDevice Tree bindings for Freescale DCU DRM Driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be one of 5*4882a593Smuzhiyun * "fsl,ls1021a-dcu". 6*4882a593Smuzhiyun * "fsl,vf610-dcu". 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- reg: Address and length of the register set for dcu. 9*4882a593Smuzhiyun- clocks: Handle to "dcu" and "pix" clock (in the order below) 10*4882a593Smuzhiyun This can be the same clock (e.g. LS1021a) 11*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 12*4882a593Smuzhiyun- clock-names: Should be "dcu" and "pix" 13*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 14*4882a593Smuzhiyun- big-endian Boolean property, LS1021A DCU registers are big-endian. 15*4882a593Smuzhiyun- port Video port for the panel output 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunOptional properties: 18*4882a593Smuzhiyun- fsl,tcon: The phandle to the timing controller node. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExamples: 21*4882a593Smuzhiyundcu: dcu@2ce0000 { 22*4882a593Smuzhiyun compatible = "fsl,ls1021a-dcu"; 23*4882a593Smuzhiyun reg = <0x0 0x2ce0000 0x0 0x10000>; 24*4882a593Smuzhiyun clocks = <&platform_clk 0>, <&platform_clk 0>; 25*4882a593Smuzhiyun clock-names = "dcu", "pix"; 26*4882a593Smuzhiyun big-endian; 27*4882a593Smuzhiyun fsl,tcon = <&tcon>; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun port { 30*4882a593Smuzhiyun dcu_out: endpoint { 31*4882a593Smuzhiyun remote-endpoint = <&panel_out>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun}; 35