1*4882a593Smuzhiyun* Faraday TV Encoder TVE200 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible: must be one of: 6*4882a593Smuzhiyun "faraday,tve200" 7*4882a593Smuzhiyun "cortina,gemini-tvc", "faraday,tve200" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- reg: base address and size of the control registers block 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun- interrupts: contains an interrupt specifier for the interrupt 12*4882a593Smuzhiyun line from the TVE200 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun- clock-names: should contain "PCLK" for the clock line clocking the 15*4882a593Smuzhiyun silicon and "TVE" for the 27MHz clock to the video driver 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun- clocks: contains phandle and clock specifier pairs for the entries 18*4882a593Smuzhiyun in the clock-names property. See 19*4882a593Smuzhiyun Documentation/devicetree/bindings/clock/clock-bindings.txt 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunOptional properties: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun- resets: contains the reset line phandle for the block 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunRequired sub-nodes: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun- port: describes LCD panel signals, following the common binding 28*4882a593Smuzhiyun for video transmitter interfaces; see 29*4882a593Smuzhiyun Documentation/devicetree/bindings/media/video-interfaces.txt 30*4882a593Smuzhiyun This port should have the properties: 31*4882a593Smuzhiyun reg = <0>; 32*4882a593Smuzhiyun It should have one endpoint connected to a remote endpoint where 33*4882a593Smuzhiyun the display is connected. 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunExample: 36*4882a593Smuzhiyun 37*4882a593Smuzhiyundisplay-controller@6a000000 { 38*4882a593Smuzhiyun #address-cells = <1>; 39*4882a593Smuzhiyun #size-cells = <0>; 40*4882a593Smuzhiyun compatible = "faraday,tve200"; 41*4882a593Smuzhiyun reg = <0x6a000000 0x1000>; 42*4882a593Smuzhiyun interrupts = <13 IRQ_TYPE_EDGE_RISING>; 43*4882a593Smuzhiyun resets = <&syscon GEMINI_RESET_TVC>; 44*4882a593Smuzhiyun clocks = <&syscon GEMINI_CLK_GATE_TVC>, 45*4882a593Smuzhiyun <&syscon GEMINI_CLK_TVC>; 46*4882a593Smuzhiyun clock-names = "PCLK", "TVE"; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun port@0 { 49*4882a593Smuzhiyun reg = <0>; 50*4882a593Smuzhiyun display_out: endpoint { 51*4882a593Smuzhiyun remote-endpoint = <&panel_in>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun}; 55