1*4882a593SmuzhiyunDevice-Tree bindings for drm hdmi driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: value should be one among the following: 5*4882a593Smuzhiyun 1) "samsung,exynos4210-hdmi" 6*4882a593Smuzhiyun 2) "samsung,exynos4212-hdmi" 7*4882a593Smuzhiyun 3) "samsung,exynos5420-hdmi" 8*4882a593Smuzhiyun 4) "samsung,exynos5433-hdmi" 9*4882a593Smuzhiyun- reg: physical base address of the hdmi and length of memory mapped 10*4882a593Smuzhiyun region. 11*4882a593Smuzhiyun- interrupts: interrupt number to the cpu. 12*4882a593Smuzhiyun- hpd-gpios: following information about the hotplug gpio pin. 13*4882a593Smuzhiyun a) phandle of the gpio controller node. 14*4882a593Smuzhiyun b) pin number within the gpio controller. 15*4882a593Smuzhiyun c) optional flags and pull up/down. 16*4882a593Smuzhiyun- ddc: phandle to the hdmi ddc node 17*4882a593Smuzhiyun- phy: phandle to the hdmi phy node 18*4882a593Smuzhiyun- samsung,syscon-phandle: phandle for system controller node for PMU. 19*4882a593Smuzhiyun- #sound-dai-cells: should be 0. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunRequired properties for Exynos 4210, 4212, 5420 and 5433: 22*4882a593Smuzhiyun- clocks: list of clock IDs from SoC clock driver. 23*4882a593Smuzhiyun a) hdmi: Gate of HDMI IP bus clock. 24*4882a593Smuzhiyun b) sclk_hdmi: Gate of HDMI special clock. 25*4882a593Smuzhiyun c) sclk_pixel: Pixel special clock, one of the two possible inputs of 26*4882a593Smuzhiyun HDMI clock mux. 27*4882a593Smuzhiyun d) sclk_hdmiphy: HDMI PHY clock output, one of two possible inputs of 28*4882a593Smuzhiyun HDMI clock mux. 29*4882a593Smuzhiyun e) mout_hdmi: It is required by the driver to switch between the 2 30*4882a593Smuzhiyun parents i.e. sclk_pixel and sclk_hdmiphy. If hdmiphy is stable 31*4882a593Smuzhiyun after configuration, parent is set to sclk_hdmiphy else 32*4882a593Smuzhiyun sclk_pixel. 33*4882a593Smuzhiyun- clock-names: aliases as per driver requirements for above clock IDs: 34*4882a593Smuzhiyun "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy" and "mout_hdmi". 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunRequired properties for Exynos 5433: 37*4882a593Smuzhiyun- clocks: list of clock specifiers according to common clock bindings. 38*4882a593Smuzhiyun a) hdmi_pclk: Gate of HDMI IP APB bus. 39*4882a593Smuzhiyun b) hdmi_i_pclk: Gate of HDMI-PHY IP APB bus. 40*4882a593Smuzhiyun d) i_tmds_clk: Gate of HDMI TMDS clock. 41*4882a593Smuzhiyun e) i_pixel_clk: Gate of HDMI pixel clock. 42*4882a593Smuzhiyun f) i_spdif_clk: Gate of HDMI SPDIF clock. 43*4882a593Smuzhiyun g) oscclk: Oscillator clock, used as parent of following *_user clocks 44*4882a593Smuzhiyun in case HDMI-PHY is not operational. 45*4882a593Smuzhiyun h) tmds_clko: TMDS clock generated by HDMI-PHY. 46*4882a593Smuzhiyun i) tmds_clko_user: MUX used to switch between oscclk and tmds_clko, 47*4882a593Smuzhiyun respectively if HDMI-PHY is off and operational. 48*4882a593Smuzhiyun j) pixel_clko: Pixel clock generated by HDMI-PHY. 49*4882a593Smuzhiyun k) pixel_clko_user: MUX used to switch between oscclk and pixel_clko, 50*4882a593Smuzhiyun respectively if HDMI-PHY is off and operational. 51*4882a593Smuzhiyun- clock-names: aliases for above clock specfiers. 52*4882a593Smuzhiyun- samsung,sysreg: handle to syscon used to control the system registers. 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunExample: 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun hdmi { 57*4882a593Smuzhiyun compatible = "samsung,exynos4212-hdmi"; 58*4882a593Smuzhiyun reg = <0x14530000 0x100000>; 59*4882a593Smuzhiyun interrupts = <0 95 0>; 60*4882a593Smuzhiyun hpd-gpios = <&gpx3 7 1>; 61*4882a593Smuzhiyun ddc = <&hdmi_ddc_node>; 62*4882a593Smuzhiyun phy = <&hdmi_phy_node>; 63*4882a593Smuzhiyun samsung,syscon-phandle = <&pmu_system_controller>; 64*4882a593Smuzhiyun }; 65