1*4882a593SmuzhiyunDevice-Tree bindings for Samsung Exynos7 SoC display controller (DECON) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunDECON (Display and Enhancement Controller) is the Display Controller for the 4*4882a593SmuzhiyunExynos7 series of SoCs which transfers the image data from a video memory 5*4882a593Smuzhiyunbuffer to an external LCD interface. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible: value should be "samsung,exynos7-decon"; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun- reg: physical base address and length of the DECON registers set. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun- interrupts: should contain a list of all DECON IP block interrupts in the 13*4882a593Smuzhiyun order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier 14*4882a593Smuzhiyun format depends on the interrupt controller used. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- interrupt-names: should contain the interrupt names: "fifo", "vsync", 17*4882a593Smuzhiyun "lcd_sys", in the same order as they were listed in the interrupts 18*4882a593Smuzhiyun property. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun- pinctrl-0: pin control group to be used for this controller. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun- pinctrl-names: must contain a "default" entry. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun- clocks: must include clock specifiers corresponding to entries in the 25*4882a593Smuzhiyun clock-names property. 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun- clock-names: list of clock names sorted in the same order as the clocks 28*4882a593Smuzhiyun property. Must contain "pclk_decon0", "aclk_decon0", 29*4882a593Smuzhiyun "decon0_eclk", "decon0_vclk". 30*4882a593Smuzhiyun- i80-if-timings: timing configuration for lcd i80 interface support. 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunOptional Properties: 33*4882a593Smuzhiyun- power-domains: a phandle to DECON power domain node. 34*4882a593Smuzhiyun- display-timings: timing settings for DECON, as described in document [1]. 35*4882a593Smuzhiyun Can be used in case timings cannot be provided otherwise 36*4882a593Smuzhiyun or to override timings provided by the panel. 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunExample: 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunSoC specific DT entry: 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun decon@13930000 { 45*4882a593Smuzhiyun compatible = "samsung,exynos7-decon"; 46*4882a593Smuzhiyun interrupt-parent = <&combiner>; 47*4882a593Smuzhiyun reg = <0x13930000 0x1000>; 48*4882a593Smuzhiyun interrupt-names = "lcd_sys", "vsync", "fifo"; 49*4882a593Smuzhiyun interrupts = <0 188 0>, <0 189 0>, <0 190 0>; 50*4882a593Smuzhiyun clocks = <&clock_disp PCLK_DECON_INT>, 51*4882a593Smuzhiyun <&clock_disp ACLK_DECON_INT>, 52*4882a593Smuzhiyun <&clock_disp SCLK_DECON_INT_ECLK>, 53*4882a593Smuzhiyun <&clock_disp SCLK_DECON_INT_EXTCLKPLL>; 54*4882a593Smuzhiyun clock-names = "pclk_decon0", "aclk_decon0", "decon0_eclk", 55*4882a593Smuzhiyun "decon0_vclk"; 56*4882a593Smuzhiyun status = "disabled"; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunBoard specific DT entry: 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun decon@13930000 { 62*4882a593Smuzhiyun pinctrl-0 = <&lcd_clk &pwm1_out>; 63*4882a593Smuzhiyun pinctrl-names = "default"; 64*4882a593Smuzhiyun status = "okay"; 65*4882a593Smuzhiyun }; 66