1*4882a593SmuzhiyunDevice-Tree bindings for Samsung Exynos SoC display controller (DECON) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunDECON (Display and Enhancement Controller) is the Display Controller for the 4*4882a593SmuzhiyunExynos series of SoCs which transfers the image data from a video memory 5*4882a593Smuzhiyunbuffer to an external LCD interface. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible: value should be one of: 9*4882a593Smuzhiyun "samsung,exynos5433-decon", "samsung,exynos5433-decon-tv"; 10*4882a593Smuzhiyun- reg: physical base address and length of the DECON registers set. 11*4882a593Smuzhiyun- interrupt-names: should contain the interrupt names depending on mode of work: 12*4882a593Smuzhiyun video mode: "vsync", 13*4882a593Smuzhiyun command mode: "lcd_sys", 14*4882a593Smuzhiyun command mode with software trigger: "lcd_sys", "te". 15*4882a593Smuzhiyun- interrupts or interrupts-extended: list of interrupt specifiers corresponding 16*4882a593Smuzhiyun to names privided in interrupt-names, as described in 17*4882a593Smuzhiyun interrupt-controller/interrupts.txt 18*4882a593Smuzhiyun- clocks: must include clock specifiers corresponding to entries in the 19*4882a593Smuzhiyun clock-names property. 20*4882a593Smuzhiyun- clock-names: list of clock names sorted in the same order as the clocks 21*4882a593Smuzhiyun property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x", 22*4882a593Smuzhiyun "aclk_xiu_decon0x", "pclk_smmu_decon0x", "aclk_smmu_decon1x", 23*4882a593Smuzhiyun "aclk_xiu_decon1x", "pclk_smmu_decon1x", clk_decon_vclk", 24*4882a593Smuzhiyun "sclk_decon_eclk" 25*4882a593Smuzhiyun- ports: contains a port which is connected to mic node. address-cells and 26*4882a593Smuzhiyun size-cells must 1 and 0, respectively. 27*4882a593Smuzhiyun- port: contains an endpoint node which is connected to the endpoint in the mic 28*4882a593Smuzhiyun node. The reg value muset be 0. 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunExample: 31*4882a593SmuzhiyunSoC specific DT entry: 32*4882a593Smuzhiyundecon: decon@13800000 { 33*4882a593Smuzhiyun compatible = "samsung,exynos5433-decon"; 34*4882a593Smuzhiyun reg = <0x13800000 0x2104>; 35*4882a593Smuzhiyun clocks = <&cmu_disp CLK_ACLK_DECON>, <&cmu_disp CLK_ACLK_SMMU_DECON0X>, 36*4882a593Smuzhiyun <&cmu_disp CLK_ACLK_XIU_DECON0X>, 37*4882a593Smuzhiyun <&cmu_disp CLK_PCLK_SMMU_DECON0X>, 38*4882a593Smuzhiyun <&cmu_disp CLK_ACLK_SMMU_DECON1X>, 39*4882a593Smuzhiyun <&cmu_disp CLK_ACLK_XIU_DECON1X>, 40*4882a593Smuzhiyun <&cmu_disp CLK_PCLK_SMMU_DECON1X>, 41*4882a593Smuzhiyun <&cmu_disp CLK_SCLK_DECON_VCLK>, 42*4882a593Smuzhiyun <&cmu_disp CLK_SCLK_DECON_ECLK>; 43*4882a593Smuzhiyun clock-names = "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x", 44*4882a593Smuzhiyun "pclk_smmu_decon0x", "aclk_smmu_decon1x", "aclk_xiu_decon1x", 45*4882a593Smuzhiyun "pclk_smmu_decon1x", "sclk_decon_vclk", "sclk_decon_eclk"; 46*4882a593Smuzhiyun interrupt-names = "vsync", "lcd_sys"; 47*4882a593Smuzhiyun interrupts = <0 202 0>, <0 203 0>; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun ports { 50*4882a593Smuzhiyun #address-cells = <1>; 51*4882a593Smuzhiyun #size-cells = <0>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun port@0 { 54*4882a593Smuzhiyun reg = <0>; 55*4882a593Smuzhiyun decon_to_mic: endpoint { 56*4882a593Smuzhiyun remote-endpoint = <&mic_to_decon>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun}; 61