1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi86.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: SN65DSI86 DSI to eDP bridge chip 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Sandeep Panda <spanda@codeaurora.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP. 14*4882a593Smuzhiyun https://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun const: ti,sn65dsi86 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reg: 21*4882a593Smuzhiyun enum: [ 0x2c, 0x2d ] 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun enable-gpios: 24*4882a593Smuzhiyun maxItems: 1 25*4882a593Smuzhiyun description: GPIO specifier for bridge_en pin (active high). 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun suspend-gpios: 28*4882a593Smuzhiyun maxItems: 1 29*4882a593Smuzhiyun description: GPIO specifier for GPIO1 pin on bridge (active low). 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun no-hpd: 32*4882a593Smuzhiyun type: boolean 33*4882a593Smuzhiyun description: 34*4882a593Smuzhiyun Set if the HPD line on the bridge isn't hooked up to anything or is 35*4882a593Smuzhiyun otherwise unusable. 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun vccio-supply: 38*4882a593Smuzhiyun description: A 1.8V supply that powers the digital IOs. 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun vpll-supply: 41*4882a593Smuzhiyun description: A 1.8V supply that powers the DisplayPort PLL. 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun vcca-supply: 44*4882a593Smuzhiyun description: A 1.2V supply that powers the analog circuits. 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun vcc-supply: 47*4882a593Smuzhiyun description: A 1.2V supply that powers the digital core. 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun interrupts: 50*4882a593Smuzhiyun maxItems: 1 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun clocks: 53*4882a593Smuzhiyun maxItems: 1 54*4882a593Smuzhiyun description: 55*4882a593Smuzhiyun Clock specifier for input reference clock. The reference clock rate must 56*4882a593Smuzhiyun be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz. 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun clock-names: 59*4882a593Smuzhiyun const: refclk 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun gpio-controller: true 62*4882a593Smuzhiyun '#gpio-cells': 63*4882a593Smuzhiyun const: 2 64*4882a593Smuzhiyun description: 65*4882a593Smuzhiyun First cell is pin number, second cell is flags. GPIO pin numbers are 66*4882a593Smuzhiyun 1-based to match the datasheet. See ../../gpio/gpio.txt for more 67*4882a593Smuzhiyun information. 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun '#pwm-cells': 70*4882a593Smuzhiyun const: 1 71*4882a593Smuzhiyun description: See ../../pwm/pwm.yaml for description of the cell formats. 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun ports: 74*4882a593Smuzhiyun type: object 75*4882a593Smuzhiyun additionalProperties: false 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun properties: 78*4882a593Smuzhiyun "#address-cells": 79*4882a593Smuzhiyun const: 1 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun "#size-cells": 82*4882a593Smuzhiyun const: 0 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun port@0: 85*4882a593Smuzhiyun type: object 86*4882a593Smuzhiyun additionalProperties: false 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun description: 89*4882a593Smuzhiyun Video port for MIPI DSI input 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun properties: 92*4882a593Smuzhiyun reg: 93*4882a593Smuzhiyun const: 0 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun endpoint: 96*4882a593Smuzhiyun type: object 97*4882a593Smuzhiyun additionalProperties: false 98*4882a593Smuzhiyun properties: 99*4882a593Smuzhiyun remote-endpoint: true 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun required: 102*4882a593Smuzhiyun - reg 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun port@1: 105*4882a593Smuzhiyun type: object 106*4882a593Smuzhiyun additionalProperties: false 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun description: 109*4882a593Smuzhiyun Video port for eDP output (panel or connector). 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun properties: 112*4882a593Smuzhiyun reg: 113*4882a593Smuzhiyun const: 1 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun endpoint: 116*4882a593Smuzhiyun type: object 117*4882a593Smuzhiyun additionalProperties: false 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun properties: 120*4882a593Smuzhiyun remote-endpoint: true 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun data-lanes: 123*4882a593Smuzhiyun oneOf: 124*4882a593Smuzhiyun - minItems: 1 125*4882a593Smuzhiyun maxItems: 1 126*4882a593Smuzhiyun uniqueItems: true 127*4882a593Smuzhiyun items: 128*4882a593Smuzhiyun enum: 129*4882a593Smuzhiyun - 0 130*4882a593Smuzhiyun - 1 131*4882a593Smuzhiyun description: 132*4882a593Smuzhiyun If you have 1 logical lane the bridge supports routing 133*4882a593Smuzhiyun to either port 0 or port 1. Port 0 is suggested. 134*4882a593Smuzhiyun See ../../media/video-interface.txt for details. 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun - minItems: 2 137*4882a593Smuzhiyun maxItems: 2 138*4882a593Smuzhiyun uniqueItems: true 139*4882a593Smuzhiyun items: 140*4882a593Smuzhiyun enum: 141*4882a593Smuzhiyun - 0 142*4882a593Smuzhiyun - 1 143*4882a593Smuzhiyun description: 144*4882a593Smuzhiyun If you have 2 logical lanes the bridge supports 145*4882a593Smuzhiyun reordering but only on physical ports 0 and 1. 146*4882a593Smuzhiyun See ../../media/video-interface.txt for details. 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun - minItems: 4 149*4882a593Smuzhiyun maxItems: 4 150*4882a593Smuzhiyun uniqueItems: true 151*4882a593Smuzhiyun items: 152*4882a593Smuzhiyun enum: 153*4882a593Smuzhiyun - 0 154*4882a593Smuzhiyun - 1 155*4882a593Smuzhiyun - 2 156*4882a593Smuzhiyun - 3 157*4882a593Smuzhiyun description: 158*4882a593Smuzhiyun If you have 4 logical lanes the bridge supports 159*4882a593Smuzhiyun reordering in any way. 160*4882a593Smuzhiyun See ../../media/video-interface.txt for details. 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun lane-polarities: 163*4882a593Smuzhiyun minItems: 1 164*4882a593Smuzhiyun maxItems: 4 165*4882a593Smuzhiyun items: 166*4882a593Smuzhiyun enum: 167*4882a593Smuzhiyun - 0 168*4882a593Smuzhiyun - 1 169*4882a593Smuzhiyun description: See ../../media/video-interface.txt 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun dependencies: 172*4882a593Smuzhiyun lane-polarities: [data-lanes] 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun required: 175*4882a593Smuzhiyun - reg 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun required: 178*4882a593Smuzhiyun - "#address-cells" 179*4882a593Smuzhiyun - "#size-cells" 180*4882a593Smuzhiyun - port@0 181*4882a593Smuzhiyun - port@1 182*4882a593Smuzhiyun 183*4882a593Smuzhiyunrequired: 184*4882a593Smuzhiyun - compatible 185*4882a593Smuzhiyun - reg 186*4882a593Smuzhiyun - enable-gpios 187*4882a593Smuzhiyun - vccio-supply 188*4882a593Smuzhiyun - vpll-supply 189*4882a593Smuzhiyun - vcca-supply 190*4882a593Smuzhiyun - vcc-supply 191*4882a593Smuzhiyun - ports 192*4882a593Smuzhiyun 193*4882a593SmuzhiyunadditionalProperties: false 194*4882a593Smuzhiyun 195*4882a593Smuzhiyunexamples: 196*4882a593Smuzhiyun - | 197*4882a593Smuzhiyun #include <dt-bindings/clock/qcom,rpmh.h> 198*4882a593Smuzhiyun #include <dt-bindings/gpio/gpio.h> 199*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/irq.h> 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun i2c { 202*4882a593Smuzhiyun #address-cells = <1>; 203*4882a593Smuzhiyun #size-cells = <0>; 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun bridge@2d { 206*4882a593Smuzhiyun compatible = "ti,sn65dsi86"; 207*4882a593Smuzhiyun reg = <0x2d>; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun interrupt-parent = <&tlmm>; 210*4882a593Smuzhiyun interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun vpll-supply = <&src_pp1800_s4a>; 215*4882a593Smuzhiyun vccio-supply = <&src_pp1800_s4a>; 216*4882a593Smuzhiyun vcca-supply = <&src_pp1200_l2a>; 217*4882a593Smuzhiyun vcc-supply = <&src_pp1200_l2a>; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun clocks = <&rpmhcc RPMH_LN_BB_CLK2>; 220*4882a593Smuzhiyun clock-names = "refclk"; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun no-hpd; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun ports { 225*4882a593Smuzhiyun #address-cells = <1>; 226*4882a593Smuzhiyun #size-cells = <0>; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun port@0 { 229*4882a593Smuzhiyun reg = <0>; 230*4882a593Smuzhiyun endpoint { 231*4882a593Smuzhiyun remote-endpoint = <&dsi0_out>; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun port@1 { 236*4882a593Smuzhiyun reg = <1>; 237*4882a593Smuzhiyun endpoint { 238*4882a593Smuzhiyun remote-endpoint = <&panel_in_edp>; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun }; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun }; 243*4882a593Smuzhiyun }; 244*4882a593Smuzhiyun - | 245*4882a593Smuzhiyun #include <dt-bindings/clock/qcom,rpmh.h> 246*4882a593Smuzhiyun #include <dt-bindings/gpio/gpio.h> 247*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/irq.h> 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun i2c { 250*4882a593Smuzhiyun #address-cells = <1>; 251*4882a593Smuzhiyun #size-cells = <0>; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun bridge@2d { 254*4882a593Smuzhiyun compatible = "ti,sn65dsi86"; 255*4882a593Smuzhiyun reg = <0x2d>; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun enable-gpios = <&msmgpio 33 GPIO_ACTIVE_HIGH>; 258*4882a593Smuzhiyun suspend-gpios = <&msmgpio 34 GPIO_ACTIVE_LOW>; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun vccio-supply = <&pm8916_l17>; 263*4882a593Smuzhiyun vcca-supply = <&pm8916_l6>; 264*4882a593Smuzhiyun vpll-supply = <&pm8916_l17>; 265*4882a593Smuzhiyun vcc-supply = <&pm8916_l6>; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun clock-names = "refclk"; 268*4882a593Smuzhiyun clocks = <&input_refclk>; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun ports { 271*4882a593Smuzhiyun #address-cells = <1>; 272*4882a593Smuzhiyun #size-cells = <0>; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun port@0 { 275*4882a593Smuzhiyun reg = <0>; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun edp_bridge_in: endpoint { 278*4882a593Smuzhiyun remote-endpoint = <&dsi_out>; 279*4882a593Smuzhiyun }; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun port@1 { 283*4882a593Smuzhiyun reg = <1>; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun edp_bridge_out: endpoint { 286*4882a593Smuzhiyun data-lanes = <2 1 3 0>; 287*4882a593Smuzhiyun lane-polarities = <0 1 0 1>; 288*4882a593Smuzhiyun remote-endpoint = <&edp_panel_in>; 289*4882a593Smuzhiyun }; 290*4882a593Smuzhiyun }; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun }; 294