1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/bridge/thine,thc63lvd1024.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Thine Electronics THC63LVD1024 LVDS Decoder 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Jacopo Mondi <jacopo+renesas@jmondi.org> 11*4882a593Smuzhiyun - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS 15*4882a593Smuzhiyun streams to parallel data outputs. The chip supports single/dual input/output 16*4882a593Smuzhiyun modes, handling up to two LVDS input streams and up to two digital CMOS/TTL 17*4882a593Smuzhiyun outputs. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun Single or dual operation mode, output data mapping and DDR output modes are 20*4882a593Smuzhiyun configured through input signals and the chip does not expose any control 21*4882a593Smuzhiyun bus. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyunproperties: 24*4882a593Smuzhiyun compatible: 25*4882a593Smuzhiyun const: thine,thc63lvd1024 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun ports: 28*4882a593Smuzhiyun type: object 29*4882a593Smuzhiyun description: | 30*4882a593Smuzhiyun This device has four video ports. Their connections are modeled using the 31*4882a593Smuzhiyun OF graph bindings specified in Documentation/devicetree/bindings/graph.txt. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun The device can operate in single-link mode or dual-link mode. In 34*4882a593Smuzhiyun single-link mode, all pixels are received on port@0, and port@1 shall not 35*4882a593Smuzhiyun contain any endpoint. In dual-link mode, even-numbered pixels are 36*4882a593Smuzhiyun received on port@0 and odd-numbered pixels on port@1, and both port@0 and 37*4882a593Smuzhiyun port@1 shall contain endpoints. 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun properties: 40*4882a593Smuzhiyun '#address-cells': 41*4882a593Smuzhiyun const: 1 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun '#size-cells': 44*4882a593Smuzhiyun const: 0 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun port@0: 47*4882a593Smuzhiyun type: object 48*4882a593Smuzhiyun description: First LVDS input port 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun port@1: 51*4882a593Smuzhiyun type: object 52*4882a593Smuzhiyun description: Second LVDS input port 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun port@2: 55*4882a593Smuzhiyun type: object 56*4882a593Smuzhiyun description: First digital CMOS/TTL parallel output 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun port@3: 59*4882a593Smuzhiyun type: object 60*4882a593Smuzhiyun description: Second digital CMOS/TTL parallel output 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun required: 63*4882a593Smuzhiyun - port@0 64*4882a593Smuzhiyun - port@2 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun additionalProperties: false 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun oe-gpios: 69*4882a593Smuzhiyun maxItems: 1 70*4882a593Smuzhiyun description: Output enable GPIO signal, pin name "OE", active high. 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun powerdown-gpios: 73*4882a593Smuzhiyun maxItems: 1 74*4882a593Smuzhiyun description: Power down GPIO signal, pin name "/PDWN", active low. 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun vcc-supply: 77*4882a593Smuzhiyun maxItems: 1 78*4882a593Smuzhiyun description: 79*4882a593Smuzhiyun Power supply for the TTL output, TTL CLOCKOUT signal, LVDS input, PLL and 80*4882a593Smuzhiyun digital circuitry. 81*4882a593Smuzhiyun 82*4882a593Smuzhiyunrequired: 83*4882a593Smuzhiyun - compatible 84*4882a593Smuzhiyun - ports 85*4882a593Smuzhiyun - vcc-supply 86*4882a593Smuzhiyun 87*4882a593SmuzhiyunadditionalProperties: false 88*4882a593Smuzhiyun 89*4882a593Smuzhiyunexamples: 90*4882a593Smuzhiyun - | 91*4882a593Smuzhiyun #include <dt-bindings/gpio/gpio.h> 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun lvds-decoder { 94*4882a593Smuzhiyun compatible = "thine,thc63lvd1024"; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun vcc-supply = <®_lvds_vcc>; 97*4882a593Smuzhiyun powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun ports { 100*4882a593Smuzhiyun #address-cells = <1>; 101*4882a593Smuzhiyun #size-cells = <0>; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun port@0 { 104*4882a593Smuzhiyun reg = <0>; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun lvds_dec_in_0: endpoint { 107*4882a593Smuzhiyun remote-endpoint = <&lvds_out>; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun port@2 { 112*4882a593Smuzhiyun reg = <2>; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun lvds_dec_out_2: endpoint { 115*4882a593Smuzhiyun remote-endpoint = <&adv7511_in>; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun... 122